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2021-05-05replace `spbtr` with `satp` (#241)Saleem Abdulrasool1-1/+1
The LLVM IAS currently does not support the older spelling for the CSR. Update the references to the modern name.
2021-03-29M-mode code doesn't need access to pk's page tableAndrew Waterman1-1/+0
2020-12-15Add support for the UART interface on the LiteX SoC (#230)gsomlo1-0/+2
Tested using the RocketChip CPU option. (see https://github.com/enjoy-digital/litex) Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-07-31Don't perform 64-bit accesses to the PLIC (#205)Alexander Richardson1-3/+3
Recent QEMU will fault for 8-byte accesses. Use a uint32_t instead of uintptr_t to avoid those problems.
2020-01-13Enable vector unit if present (continuation of ↵Andrew Waterman1-2/+6
77a5df569451571d608650a34183d53df99790ec)
2020-01-11Enable vector unit if presentAndrew Waterman1-0/+4
2019-12-06Only prohibit float32-only when FP emulation is enabledAndrew Waterman1-2/+9
2019-06-11Check for 'U' extension before accessing 'mcounteren' CSRGabriel L. Somlo1-1/+2
On 64-bit Rocket with 'DefaultFPGAConfig' (using 'WithNSmallCores'), the 'U' extension is not supported, and accessing 'mcounteren' would trigger an 'Illegal Instruction' trap. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-01-04Set up PMP earlier, so it can be overridden laterAndrew Waterman1-5/+2
2018-12-02Revert "Avoid writing reserved values to pmpaddr CSR"Andrew Waterman1-2/+1
This reverts commit 7bee30c1ff56975041ffc67cd0170d7477aba865. All ones is no longer "reserved", so the old code is OK.
2018-11-20Fix the calculation for the number of interrupt enable wordsLogan Gunthorpe1-1/+2
The number of interrupt enable words should be the number of devices divided by the number of bits per word (not the number of bytes per word) and it should round up. Without this fix, when using a larger number of interrupts, the user will see a number of errors in qemu of the form: plic: invalid register write: %08x Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
2018-09-23Avoid writing reserved values to pmpaddr CSRAndrew Waterman1-1/+2
2018-07-12minit: Move pmp setup code to a separate function to avoid duplicating codeHesham Almatary1-11/+7
Currently it's being used by both enter_supervisor_mode and enter_machine_mode
2018-07-12bbl: boot payload in machine mode when --enable-boot-machine is passedHesham Almatary1-0/+26
2018-07-09Properly license all nontrivial filesAndrew Waterman1-0/+2
2018-05-22RISC-V: Support separate firmware and kernel payloadMichael Clark1-0/+3
Support for separate firmware and kernel payload is added by updating BBL to read optional preloaded kernel address attributes from device-tree using a similar mechanism to that used to pass init ramdisk addresses to linux kernel. chosen { riscv,kernel-start = <0x00000000 0x80200000>; riscv,kernel-end = <0x00000000 0x80590634>; }; These attributes are added by QEMU and read by BBL when combining -bios <firmware-image> and -kernel <kernel-image> options. e.g. $ qemu-system-riscv64 -machine virt -bios bbl -kernel vmlinux With this change, bbl can be compiled without --with-payload and the dummy payload alignment is altered to make the memory footprint of the firmware-only bbl smaller. The dummy payload message is updated to indicate the alternative load method. This load method could also be supported by a first stage boot loader that reads seperate firmware and kernel from SPI flash. The main advantage of this new mechanism is that it eases kernel development by avoiding the riscv-pk packaging step after kernel builds, makes building per repository artefacts for CI simpler, and mimics bootloaders on other platforms that can load a kernel image file directly. Ultimately BBL should use an SPI driver to load the kernel image however this mechanism supports use cases such such as QEMU's -bios, -kernel and -initrd options following examples from other platforms that pass kernel entry to firmware via device-tree. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-21machine,minit: initialize emulated FCSR in enter_supervisor_mode() (#106)Zihao Yu1-0/+4
* If BBL emulates the FPU, the trap handler will load emulated FCSR from x0's save slot into tp. The emulated FCSR should be initialized, else the field of rounding mode will contain garbage codes. This will lead to raising SIGABRT for a user mode program which tries to print a floating point variable. In glibc, __printf_fp_l() (defined in riscv-glibc/stdio-common/printf_fp.c) will call round_away() (defined in riscv-glibc/include/rounding-mode.h). With a garbage rounding mode in emulated FCSR, round_away() may call abort().
2018-05-15Fix for missing supervisor mode when running on E51 (#96)Jim Straus1-3/+10
The E51 core on the U54-MC lacks supervisor mode, thus the plic_s_ie and plic_s_thresh are NULL when running on this core. This adds checks for this case.
2018-03-20minit: insert printm as work-around for a race conditionWesley W. Terpstra1-0/+1
Reboot does not work reliably without this.
2018-01-09Remove the repeating bitmask of medeleg register (#74)Zong Li1-1/+0
2017-12-12Add a 16550 UART driver to back the SBI consolePalmer Dabbelt1-0/+2
QEMU currently provides the console via HTIF and the SBI. That's a bit messy because BBL polls for serial input, which means that typing too quickly loses characters. While QEMU has a standard 16550 device model, there's no way to have two consoles share the console in QEMU (as they'd step all over each other) so that means we can't have both the HTIF console and the 16550 console. With this patch, QEMU can be changed to use a 16650 instead of the HTIF for serial output. Linux will use the SBI for early printk support (which is fine, polling for output is stable) and then swap over as soon as it detects the UART. When Linux swaps it prints out the whole history, but there's probably a way to get around that. There's a few lines that are output to both, but it appears the Linux driver is close enough to ours that nothing catastrophic happens -- there's not much to the device, so hopefully that pans out on real hardware too. Once Linux swaps over to natively using the driver we get reliable console input. If you don't have the in-kernel driver then Linux never swaps over and keeps using the SBI console just like before.
2017-11-03Remove the platform interfacePalmer Dabbelt1-1/+2
We now automatically detect everything that the platform interface used to be used for, so it's now obsolete!
2017-11-02Check if we have extensions before using themPalmer Dabbelt1-5/+12
2017-11-02Initialize the UART firstPalmer Dabbelt1-3/+3
Without this I can't get printf to show me debug info during early boot.
2017-11-02Detect harts that can't boot Linux instead of hard-coding themPalmer Dabbelt1-1/+2
This checks to see if a hart can't boot Linux by looking for a compatible "mmu-type" field. If the hart can't boot Linux, then bbl masks it off.
2017-08-14finisher: support terminating sifive devices simulation (#61)Wesley W. Terpstra1-0/+4
2017-08-02Move DISABLED_HART_MASK to the platformPalmer Dabbelt1-1/+2
Some platforms can't boot Linux on all the harts. This commit allows platforms to define the set of harts that should be prevented from booting past BBL. This is essentially just a new mechanism for defining the DISABLED_HART_MASK.
2017-04-05Remove num_harts; use hart_mask exclusivelyAndrew Waterman1-1/+0
2017-04-05Rename HART_MASK to DISABLED_HART_MASK to clarify polarityAndrew Waterman1-1/+1
2017-04-05bbl: prevent named cores from bootingWesley W. Terpstra1-1/+1
2017-04-04Remove SBI console printm to speed up PK simulationAndrew Waterman1-1/+0
2017-03-31clint: move hart wakeup till after all FDT parsingWesley W. Terpstra1-2/+11
The clint was wiping out information discovered by the plic. Initialize hart stacks as they are discovered. Then fill in clint+plic info Then wake the harts.
2017-03-30New PMP encodingAndrew Waterman1-1/+1
2017-03-28plic: discovered via fdtWesley W. Terpstra1-0/+1
2017-03-27uart: add physical device driverWesley W. Terpstra1-0/+5
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-3/+3
2017-03-23Set up PMPs, permissively for nowAndrew Waterman1-0/+11
2017-03-22SBI: a0+a1 hold hartid+dtb pointer between boot loader stagesfdtWesley W. Terpstra1-9/+7
2017-03-22machine: add FDT parserWesley W. Terpstra1-7/+8
2017-03-08Don't rely on config string for basic functionalityAndrew Waterman1-1/+7
2017-02-25New counter-enable schemeAndrew Waterman1-3/+5
https://github.com/riscv/riscv-isa-manual/issues/10
2017-02-22Fix PK bootAndrew Waterman1-1/+3
2017-02-20Don't block for acks on console writesAndrew Waterman1-8/+0
2017-02-17WIP towards ECALL interface for SBIAndrew Waterman1-3/+6
2017-02-15Incorporate sptbr/sfence.vma changesAndrew Waterman1-10/+3
2016-10-25Use __riscv_flen macro to detect FP supportAndrew Waterman1-1/+1
2016-09-09Attempt to disable FPU if using no-FPU pk/bblAndrew Waterman1-2/+3
2016-07-28Don't let other harts boot before HLS is initializedAndrew Waterman1-6/+0
Use IPIs to signal them.
2016-07-05Initialize timecmp; add PRCI testAndrew Waterman1-0/+15
2016-06-05PLIC registers are 32-bit, not 16-bitAndrew Waterman1-2/+2