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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-17 01:54:41 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-17 01:54:41 -0800 |
| commit | 926b360655fd7a22413c7732faceeea21a224aa1 (patch) | |
| tree | a0fe50446c5ccbdb2aecd7945aa7025804c655e7 /machine/minit.c | |
| parent | 611290ccde8d76c1973a37d82a5d4b3e4b7b90c4 (diff) | |
| download | riscv-pk-926b360655fd7a22413c7732faceeea21a224aa1.zip riscv-pk-926b360655fd7a22413c7732faceeea21a224aa1.tar.gz riscv-pk-926b360655fd7a22413c7732faceeea21a224aa1.tar.bz2 | |
WIP towards ECALL interface for SBI
Diffstat (limited to 'machine/minit.c')
| -rw-r--r-- | machine/minit.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/machine/minit.c b/machine/minit.c index 06e8d25..0c95ea4 100644 --- a/machine/minit.c +++ b/machine/minit.c @@ -141,7 +141,7 @@ void init_other_hart() boot_other_hart(); } -void enter_supervisor_mode(void (*fn)(uintptr_t), uintptr_t stack) +void enter_supervisor_mode(void (*fn)(uintptr_t), uintptr_t arg0, uintptr_t arg1) { uintptr_t mstatus = read_csr(mstatus); mstatus = INSERT_FIELD(mstatus, MSTATUS_MPP, PRV_S); @@ -149,7 +149,10 @@ void enter_supervisor_mode(void (*fn)(uintptr_t), uintptr_t stack) write_csr(mstatus, mstatus); write_csr(mscratch, MACHINE_STACK_TOP() - MENTRY_FRAME_SIZE); write_csr(mepc, fn); - write_csr(sptbr, ((uintptr_t)root_page_table >> RISCV_PGSHIFT) | SPTBR_MODE); - asm volatile ("mv a0, %0; mv sp, %0; mret" : : "r" (stack)); + write_csr(sptbr, 0); + + register uintptr_t a0 asm ("a0") = arg0; + register uintptr_t a1 asm ("a1") = arg1; + asm volatile ("mret" : : "r" (a0), "r" (a1)); __builtin_unreachable(); } |