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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-11 17:37:24 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-11 17:37:24 +0200 |
| commit | 46cd5082c5d324bb843be35d8130aa9d44068d7d (patch) | |
| tree | 76d47a8160f3d22bf2a69dd510b41b24a2dbb0fc /machine | |
| parent | cb253a3f970b373df4390a0e7a17610556f920f3 (diff) | |
| parent | ff71b88278db63ff22b7f39d38bd952dea34f2a1 (diff) | |
| download | riscv-pk-46cd5082c5d324bb843be35d8130aa9d44068d7d.zip riscv-pk-46cd5082c5d324bb843be35d8130aa9d44068d7d.tar.gz riscv-pk-46cd5082c5d324bb843be35d8130aa9d44068d7d.tar.bz2 | |
Merge pull request #163 from gsomlo/gls-litex
Building BBL for the LiteX/Rocket SoC
Diffstat (limited to 'machine')
| -rw-r--r-- | machine/minit.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/machine/minit.c b/machine/minit.c index bb1ee6e..5ad6d92 100644 --- a/machine/minit.c +++ b/machine/minit.c @@ -30,7 +30,8 @@ static void mstatus_init() // Enable user/supervisor use of perf counters if (supports_extension('S')) write_csr(scounteren, -1); - write_csr(mcounteren, -1); + if (supports_extension('U')) + write_csr(mcounteren, -1); // Enable software interrupts write_csr(mie, MIP_MSIP); |