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authorPalmer Dabbelt <palmer@dabbelt.com>2017-12-13 17:05:42 -0800
committerPalmer Dabbelt <palmer@dabbelt.com>2017-12-13 17:05:42 -0800
commit15ff218ec04c4d8aea4bdfafd9259f158978e402 (patch)
treef90d08ad9684beafd5ea973fdcace3465cd58c94
parent3d921d3c76db3af7b9ae0b5df0f0790f26222246 (diff)
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Add __riscv_flush_icache
For BBL's purposes a local i-cache flush should be sufficient.
-rw-r--r--machine/flush_icache.c3
-rw-r--r--machine/machine.mk.in1
2 files changed, 4 insertions, 0 deletions
diff --git a/machine/flush_icache.c b/machine/flush_icache.c
new file mode 100644
index 0000000..45ba204
--- /dev/null
+++ b/machine/flush_icache.c
@@ -0,0 +1,3 @@
+void __riscv_flush_icache(void) {
+ __asm__ volatile ("fence.i");
+}
diff --git a/machine/machine.mk.in b/machine/machine.mk.in
index dc8492f..625e5bf 100644
--- a/machine/machine.mk.in
+++ b/machine/machine.mk.in
@@ -28,6 +28,7 @@ machine_c_srcs = \
uart.c \
finisher.c \
misaligned_ldst.c \
+ flush_icache.c \
machine_asm_srcs = \
mentry.S \