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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-23 20:48:21 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-23 20:49:53 -0700 |
| commit | 7bee30c1ff56975041ffc67cd0170d7477aba865 (patch) | |
| tree | 2713b95125cc5a3606f2b0bb75ca942af977a93d | |
| parent | ac2c910b18c3e36cfd85080472e78ad2fe484325 (diff) | |
| download | riscv-pk-7bee30c1ff56975041ffc67cd0170d7477aba865.zip riscv-pk-7bee30c1ff56975041ffc67cd0170d7477aba865.tar.gz riscv-pk-7bee30c1ff56975041ffc67cd0170d7477aba865.tar.bz2 | |
Avoid writing reserved values to pmpaddr CSR
| -rw-r--r-- | machine/minit.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/machine/minit.c b/machine/minit.c index 953e1ba..b8c9eac 100644 --- a/machine/minit.c +++ b/machine/minit.c @@ -191,13 +191,14 @@ static inline void setup_pmp(void) // Set up a PMP to permit access to all of memory. // Ignore the illegal-instruction trap if PMPs aren't supported. uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X; + uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1; asm volatile ("la t0, 1f\n\t" "csrrw t0, mtvec, t0\n\t" "csrw pmpaddr0, %1\n\t" "csrw pmpcfg0, %0\n\t" ".align 2\n\t" "1: csrw mtvec, t0" - : : "r" (pmpc), "r" (-1UL) : "t0"); + : : "r" (pmpc), "r" (pmpa) : "t0"); } void enter_supervisor_mode(void (*fn)(uintptr_t), uintptr_t arg0, uintptr_t arg1) |