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rocket-tools/riscv-openocd.git
FE_402_fix
__archive__
aap-sc/switch_snapshot_to_22_04
add_macos_build
autoconf
bscan_optimization
bscan_tunnel
buf_sget
build32
busy
compliance_dev
debug-log-reg-failure
deinit
dmi_read
dmstatus_version
dsp5680_build
eclipse_memory_read
eclipse_multicore_fix
examine_command
examine_unavailable_harts
examine_unavailable_harts_backup
examine_unavailable_harts_rebase
examine_unavailable_harts_squash
fence_i_fix_for_release
fix_macbuild
gd32vf103
gdb_next_port
gitignore-build
global
halt_examine
haltreq
hypervisor_translate
jlink
log_output
macbuild
macro
manual_hwbp
master
mem64
mpsse_flush
multicore
new_bscan_approach
newprogram
nohartstatus
old_fixes_and_eclipse_memory_read
old_triggers
print_port
race
rbb_cleanup
regcache
release
reset_test
reverse-resume-order
riscv
riscv-compliance
riscv-compliance-dev
s2_increment
sba_tests
set_group
static
travis-nop
update_defines
us_xds110
vector2
winbuild
wip
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batch.c
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Author
Files
Lines
2025-02-17
Merge pull request #1208 from en-sc/en-sc/pass-tap
Evgeniy Naydanov
1
-1
/
+2
2025-02-07
target/riscv: pass `jtag_tap` instead of `target`
Evgeniy Naydanov
1
-1
/
+2
2025-01-21
Fix data types around batch.{c,h}
Jan Matyas
1
-28
/
+62
2024-11-12
Merge up to fd62626dff25cf503a25040d3040b0a2bb9b2a76 from upstream
Evgeniy Naydanov
1
-2
/
+2
2024-10-20
target: riscv: remove non-trivial 'unsigned' cast
Antonio Borneo
1
-2
/
+2
2024-10-20
target: riscv: convert 'unsigned' to 'unsigned int'
Antonio Borneo
1
-3
/
+3
2024-09-26
target/riscv: DMI logging improvements
Evgeniy Naydanov
1
-54
/
+99
2024-09-23
target/riscv: move `riscv_log_dmi_scan`
Evgeniy Naydanov
1
-0
/
+78
2024-08-02
jtag: Use 'unsigned int' for 'scan_field.num_bits'
Marc Schink
1
-2
/
+2
2024-07-16
target/riscv: single DMI accesses via batch
Evgeniy Naydanov
1
-6
/
+5
2024-07-01
target/riscv: replace `info->*_delay` with `riscv_scan_delays`
Evgeniy Naydanov
1
-8
/
+8
2024-06-06
target/riscv: write registers using batch
Evgeniy Naydanov
1
-15
/
+55
2024-05-23
target/riscv: read abstract args using batch
Evgeniy Naydanov
1
-23
/
+62
2024-04-26
target/riscv: reset delays during batch scans
Evgeniy Naydanov
1
-2
/
+5
2024-04-19
target/riscv: decode DMI scans in batch access
Evgeniy Naydanov
1
-35
/
+2
2024-02-15
Fixes of review findings
Jan Matyas
1
-3
/
+7
2024-02-06
Fixes and cleanup in riscv batch and related functions
Jan Matyas
1
-42
/
+49
2024-01-26
Revert "break from long loops on shutdown request"
Evgeniy Naydanov
1
-3
/
+0
2024-01-09
break from long loops on shutdown request
Evgeniy Naydanov
1
-0
/
+3
2023-12-11
Merge pull request #959 from en-sc/en-sc/progbuf-mem-write
Tim Newsome
1
-0
/
+10
2023-12-07
target/riscv: improve error handling in `write_memory_progbuf()`
Evgeniy Naydanov
1
-0
/
+10
2023-11-16
Merge pull request #958 from riscv/set_field_get_field
Tim Newsome
1
-3
/
+1
2023-11-15
target/riscv: Replace [sg]et_field macros with functions.
Tim Newsome
1
-3
/
+1
2023-11-15
target/riscv: replace `__PRETTY_FUNCTION__` with `__func__`
Evgeniy Naydanov
1
-2
/
+2
2023-07-26
target/riscv: add dm layer
Mark Zhuang
1
-8
/
+8
2023-07-24
target/riscv: Add target logging to most logging instances
Marek Vrbka
1
-2
/
+2
2023-07-22
target/riscv: Add null pointer check before right shift for bscan tunneling.
eolson
1
-2
/
+4
2023-07-20
target/riscv: fix semantic checker warnings
Erhan Kurubas
1
-2
/
+2
2023-07-14
target/riscv: refactor read_memory_progbuf()
Evgeniy Naydanov
1
-2
/
+2
2023-06-22
Add null pointer check before right shift for bscan tunneling.
eolson
1
-2
/
+4
2023-03-16
Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream
Tim Newsome
1
-1
/
+1
2022-11-17
target/riscv: Don't always read on DMI batch write (#768)
Tim Newsome
1
-3
/
+8
2022-09-18
openocd: fix SPDX tag format for files .c
Antonio Borneo
1
-1
/
+1
2021-10-25
Upstream a whole host of RISC-V changes.
Tim Newsome
1
-7
/
+19
2021-07-24
openocd: fix simple cases of NULL comparison
Antonio Borneo
1
-1
/
+1
2020-10-14
Upstream tons of RISC-V changes.
Tim Newsome
1
-30
/
+80
2019-03-27
Lots of RISC-V improvements.
Tim Newsome
1
-18
/
+9
2018-07-24
Add RISC-V support.
Tim Newsome
1
-0
/
+172