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| author | Tim Newsome <tim@sifive.com> | 2020-01-24 14:10:04 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2020-01-24 14:52:19 -0800 |
| commit | 23a0ce22cf21427f860f9690f223e3febd5f6bf9 (patch) | |
| tree | 897fb486329987e5392395a18c15cd17573e6e2d /src/target/riscv/program.c | |
| parent | 9e80ab1f857c8a60fd4552479a4692e13d02c28d (diff) | |
| download | riscv-openocd-vector2.zip riscv-openocd-vector2.tar.gz riscv-openocd-vector2.tar.bz2 | |
Reading v* registers appears to work.vector2
Can't really test it though, because gdb doesn't print them right.
Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5
Diffstat (limited to 'src/target/riscv/program.c')
| -rw-r--r-- | src/target/riscv/program.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/target/riscv/program.c b/src/target/riscv/program.c index 8645ed6..b370401 100644 --- a/src/target/riscv/program.c +++ b/src/target/riscv/program.c @@ -56,7 +56,8 @@ int riscv_program_exec(struct riscv_program *p, struct target *t) if (riscv_program_ebreak(p) != ERROR_OK) { LOG_ERROR("Unable to write ebreak"); for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i) - LOG_ERROR("ram[%02x]: DASM(0x%08lx) [0x%08lx]", (int)i, (long)p->debug_buffer[i], (long)p->debug_buffer[i]); + LOG_ERROR("ram[%02x]: DASM(0x%08lx) [0x%08lx]", (int)i, + (long)p->debug_buffer[i], (long)p->debug_buffer[i]); return ERROR_FAIL; } |