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| author | Evgeniy Naydanov <109669442+en-sc@users.noreply.github.com> | 2025-03-10 09:22:14 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-10 09:22:14 +0300 |
| commit | c3f1566608b28d1f85b70a61c69ee624d8c8cb48 (patch) | |
| tree | b6eccebca9aaebc1cd9a73482398efb291f4945b | |
| parent | 67082829da364ad042eea12a455450d707ea4d57 (diff) | |
| parent | 45231117b8686af3b896c9645a7b5b7b3b8e1cfc (diff) | |
| download | riscv-openocd-c3f1566608b28d1f85b70a61c69ee624d8c8cb48.zip riscv-openocd-c3f1566608b28d1f85b70a61c69ee624d8c8cb48.tar.gz riscv-openocd-c3f1566608b28d1f85b70a61c69ee624d8c8cb48.tar.bz2 | |
Merge pull request #1238 from en-sc/en-sc/abits-zero
src/target/riscv: error out of the `examine()` in case `abits` is zero
| -rw-r--r-- | src/target/riscv/riscv-013.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 1c5d60e..d02059c 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1956,6 +1956,11 @@ static int examine(struct target *target) return ERROR_FAIL; } + if (info->abits == 0) { + LOG_TARGET_ERROR(target, + "dtmcs.abits is zero. Check JTAG connectivity/board power"); + return ERROR_FAIL; + } if (info->abits < RISCV013_DTMCS_ABITS_MIN) { /* The requirement for minimum DMI address width of 7 bits is part of * the RISC-V Debug spec since Jan-20-2017 (commit 03df6ee7). However, |