rocket-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
confprec	Add vsetprec instruction	Quan Nguyen	11 years
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	8 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	3 years
llvm-encodings	WIP: auto-generate llvm encoding file	Colin Schmidt	8 years
master	Add Unit Tests for shared_utils.py (#309)	Aditya Mohan	9 hours
mvp	Add vf[ls]seg(\|st)h and friends	Quan Nguyen	11 years
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	3 years
rvv	Fix config imms	Colin Schmidt	6 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	5 years