Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2016-12-21 | Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space | Kito Cheng | 1 | -1/+1 | |
2016-08-26 | Renumber misa; add performance counter CSRs | Andrew Waterman | 1 | -33/+154 | |
2016-08-25 | Re-rename trigger registers to be 1-based | Andrew Waterman | 1 | -3/+3 | |
2016-08-25 | Make hardware triggers match latest spec. | Tim Newsome | 1 | -4/+4 | |
2016-06-30 | Remove instructions from privilege spec that are already in user spec | Andrew Waterman | 1 | -5/+2 | |
2016-06-17 | Remove sasid (it's merged into sptbr now) | Andrew Waterman | 1 | -1/+0 | |
2016-06-08 | Add breakpoint CSRs | Andrew Waterman | 1 | -0/+4 | |
2016-06-01 | Add dret instruction and debug CSRs. (#5) | Tim Newsome | 1 | -0/+3 | |
2016-05-13 | Remove arg lists from latex tables | Andrew Waterman | 1 | -42/+1 | |
2016-05-02 | Remove mipi registers | Andrew Waterman | 1 | -1/+0 | |
IPI pending registers will live outside the core, so they can cause wakeup. | |||||
2016-05-02 | Remove tohost/fromhost | Andrew Waterman | 1 | -2/+0 | |
2016-04-30 | Remove mcfgaddr; change memory map | Andrew Waterman | 1 | -2/+1 | |
2016-04-30 | Remove mtimecmp | Andrew Waterman | 1 | -2/+0 | |
2016-04-30 | ERET -> xRET | Andrew Waterman | 1 | -1/+1 | |
2016-04-06 | Remove nonstandard stats, uarch CSRs | Andrew Waterman | 1 | -21/+0 | |
2016-03-03 | Update CSR encoding | Andrew Waterman | 1 | -0/+19 | |
2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -30/+14 | |
2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -16/+15 | |
2016-02-05 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -5/+4 | |
2015-11-12 | add miobase, mipi; drop send_ipi | Andrew Waterman | 1 | -1/+2 | |
2015-09-28 | In C headers, keep instructions in original input order | Andrew Waterman | 1 | -2/+2 | |
2015-09-08 | Use BitPat instead of Bits for Chisel3 | Andrew Waterman | 1 | -1/+1 | |
2015-09-08 | update to latest RVC proposal | Andrew Waterman | 1 | -2/+5 | |
2015-07-28 | Fix DECLARE_CAUSE macros | Andrew Waterman | 1 | -1/+1 | |
2015-07-05 | New machine-mode timer facility | Andrew Waterman | 1 | -1/+1 | |
2015-05-09 | Update to privileged architecture version 1.7 | Andrew Waterman | 1 | -25/+96 | |
2015-03-30 | RVC draft | Andrew Waterman | 1 | -13/+2 | |
2015-03-17 | Merge [shm]call into ecall, [shm]ret into eret | Andrew Waterman | 1 | -8/+6 | |
2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -27/+53 | |
2014-04-03 | Move stats register | Stephen Twigg | 1 | -1/+1 | |
2014-03-18 | Add rdcycleh etc. for RV32 | Andrew Waterman | 1 | -6/+22 | |
2014-03-11 | Fix syntax error in generated opcodes | Andrew Waterman | 1 | -2/+2 | |
2014-03-11 | New FP encoding | Andrew Waterman | 1 | -15/+20 | |
2014-03-06 | Add fclass.{s|d} instructions | Andrew Waterman | 1 | -2/+4 | |
2014-02-14 | Renumber uarch CSRs into custom CSR space | Andrew Waterman | 1 | -16/+16 | |
2014-02-06 | Reserve 16 uarch-specific read-only userspace counters | Andrew Waterman | 1 | -0/+16 | |
2014-01-21 | Add DECLARE_CAUSE macro | Andrew Waterman | 1 | -0/+5 | |
2014-01-21 | Auto-generate exception cause numbers | Andrew Waterman | 1 | -0/+27 | |
2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 1 | -36/+35 | |
2013-11-25 | New privileged ISA | Andrew Waterman | 1 | -15/+71 | |
2013-11-22 | add missing imm for stores | Yunsup Lee | 1 | -0/+1 | |
2013-10-29 | changes to the instr-table | Yunsup Lee | 1 | -14/+16 | |
2013-10-10 | revamp hwacha-v3 opcodes | Yunsup Lee | 1 | -2/+1 | |
2013-09-21 | Fix funct field in tables. | Andrew Waterman | 1 | -1/+1 | |
2013-09-21 | Update ISA encoding | Andrew Waterman | 1 | -191/+238 | |
2013-08-07 | hwacha v3: inst format follows the new rocket accelerator extensions | Yunsup Lee | 1 | -0/+2 | |
2013-08-06 | Rename MTFSR/MFFSR to FSSR/FRSR | Andrew Waterman | 1 | -2/+2 | |
2013-07-31 | HW ignores upper bits of fence, but SW supplies 0 | Andrew Waterman | 1 | -10/+14 | |
2013-07-26 | tweaks | Yunsup Lee | 1 | -11/+13 | |
2013-07-26 | Factor out Hwacha/RVC and rename MFTX/MXTF to FMV | Andrew Waterman | 1 | -4/+4 | |