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AgeCommit message (Expand)AuthorFilesLines
2016-12-21Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 spaceKito Cheng1-1/+1
2016-08-26Renumber misa; add performance counter CSRsAndrew Waterman1-33/+154
2016-08-25Re-rename trigger registers to be 1-basedAndrew Waterman1-3/+3
2016-08-25Make hardware triggers match latest spec.Tim Newsome1-4/+4
2016-06-30Remove instructions from privilege spec that are already in user specAndrew Waterman1-5/+2
2016-06-17Remove sasid (it's merged into sptbr now)Andrew Waterman1-1/+0
2016-06-08Add breakpoint CSRsAndrew Waterman1-0/+4
2016-06-01Add dret instruction and debug CSRs. (#5)Tim Newsome1-0/+3
2016-05-13Remove arg lists from latex tablesAndrew Waterman1-42/+1
2016-05-02Remove mipi registersAndrew Waterman1-1/+0
2016-05-02Remove tohost/fromhostAndrew Waterman1-2/+0
2016-04-30Remove mcfgaddr; change memory mapAndrew Waterman1-2/+1
2016-04-30Remove mtimecmpAndrew Waterman1-2/+0
2016-04-30ERET -> xRETAndrew Waterman1-1/+1
2016-04-06Remove nonstandard stats, uarch CSRsAndrew Waterman1-21/+0
2016-03-03Update CSR encodingAndrew Waterman1-0/+19
2016-02-28WIP on priv spec v1.9Andrew Waterman1-30/+14
2016-02-28WIP on priv spec v1.9Andrew Waterman1-16/+15
2016-02-05WIP on priv spec v1.9Andrew Waterman1-5/+4
2015-11-12add miobase, mipi; drop send_ipiAndrew Waterman1-1/+2
2015-09-28In C headers, keep instructions in original input orderAndrew Waterman1-2/+2
2015-09-08Use BitPat instead of Bits for Chisel3Andrew Waterman1-1/+1
2015-09-08update to latest RVC proposalAndrew Waterman1-2/+5
2015-07-28Fix DECLARE_CAUSE macrosAndrew Waterman1-1/+1
2015-07-05New machine-mode timer facilityAndrew Waterman1-1/+1
2015-05-09Update to privileged architecture version 1.7Andrew Waterman1-25/+96
2015-03-30RVC draftAndrew Waterman1-13/+2
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman1-8/+6
2015-03-12Update to new privileged specAndrew Waterman1-27/+53
2014-04-03Move stats registerStephen Twigg1-1/+1
2014-03-18Add rdcycleh etc. for RV32Andrew Waterman1-6/+22
2014-03-11Fix syntax error in generated opcodesAndrew Waterman1-2/+2
2014-03-11New FP encodingAndrew Waterman1-15/+20
2014-03-06Add fclass.{s|d} instructionsAndrew Waterman1-2/+4
2014-02-14Renumber uarch CSRs into custom CSR spaceAndrew Waterman1-16/+16
2014-02-06Reserve 16 uarch-specific read-only userspace countersAndrew Waterman1-0/+16
2014-01-21Add DECLARE_CAUSE macroAndrew Waterman1-0/+5
2014-01-21Auto-generate exception cause numbersAndrew Waterman1-0/+27
2013-12-09New RDCYCLE encodingAndrew Waterman1-36/+35
2013-11-25New privileged ISAAndrew Waterman1-15/+71
2013-11-22add missing imm for storesYunsup Lee1-0/+1
2013-10-29changes to the instr-tableYunsup Lee1-14/+16
2013-10-10revamp hwacha-v3 opcodesYunsup Lee1-2/+1
2013-09-21Fix funct field in tables.Andrew Waterman1-1/+1
2013-09-21Update ISA encodingAndrew Waterman1-191/+238
2013-08-07hwacha v3: inst format follows the new rocket accelerator extensionsYunsup Lee1-0/+2
2013-08-06Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman1-2/+2
2013-07-31HW ignores upper bits of fence, but SW supplies 0Andrew Waterman1-10/+14
2013-07-26tweaksYunsup Lee1-11/+13
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman1-4/+4
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