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AgeCommit message (Expand)AuthorFilesLines
2013-09-21Remove old fileAndrew Waterman1-160/+0
2013-08-06Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman1-2/+2
2013-07-31Swap J and JALR encodingsAndrew Waterman1-7/+7
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman1-127/+4
2013-07-25Refactor parse-opcodesAndrew Waterman1-285/+282
2013-04-17add auipc, lr, scAndrew Waterman1-1/+5
2012-03-24new supervisor modeAndrew Waterman1-14/+13
2012-03-18change vector fence names/encodingAndrew Waterman1-6/+4
2012-03-18clean up vector exception instructionsYunsup Lee1-7/+9
2012-03-13add more instructions for vector exception handlingYunsup Lee1-1/+4
2012-03-13add vvcfg,vtcfgYunsup Lee1-0/+2
2012-03-13opcodes cleanupYunsup Lee1-3/+2
2012-03-10slight change to vector supervisor instructionsYunsup Lee1-4/+4
2012-03-03new instructions to handle vector exceptionsYunsup Lee1-0/+6
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+273
2011-06-19Renamed packagesAndrew Waterman1-273/+0
2011-06-19[riscv-isa-run] code cleanup; added READMEAndrew Waterman1-0/+1
2011-05-15[opcodes,pk,sim,xcc] resolve a conflictYunsup Lee1-4/+4
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee1-71/+76
2011-05-13tweaked encoding of rdcycle & cousinsAndrew Waterman1-3/+6
2011-05-06[opcodes] reordered RVC instructionsAndrew Waterman1-7/+7
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman1-0/+1
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman1-1/+20
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman1-0/+2
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman1-0/+1
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman1-0/+8
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-0/+2
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-0/+1
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-3/+3
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee1-1/+1
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Yunsup Lee1-33/+69
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee1-0/+5
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee1-0/+30
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee1-0/+2
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee1-0/+4
2011-03-25[opcodes] minor opcode changesAndrew Waterman1-41/+41
2011-03-25[sim,pk,xcc,opcodes] removed fminmag/fmaxmagAndrew Waterman1-4/+0
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman1-29/+38
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman1-40/+40
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman1-3/+0
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman1-1/+2
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman1-1/+1
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman1-24/+23
2011-01-31[opcodes] fixed verilog generation for shiftsAndrew Waterman1-6/+6
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman1-1/+2
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman1-145/+143
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman1-79/+81
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-2/+0
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman1-1/+0
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee1-152/+152
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