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Adding RV128 shift opcodes changed what metadata we emit for SLLI, SRLI,
and SRAI. Thus, downstream tooling that relies on these to connote the
RV64 variants of these instructions is semantically affected.
Fix by reverting SLLI etc. to being the RV64 variants.
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This will reduce the chance that people pick the wrong shamt width.
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svadu
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It's a new year. Make the copyright clause reflect 2023.
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The Svadu extension (https://github.com/riscv/riscv-svadu) adds the
HADE bit (61) to menvcfg and henvcfg CSRs to control updating of the
A/D bits in the PTE. Provide the bit encodings for the HADE support.
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Fix issues from #153
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Fix backwards incompatibility introduced by RV128 opcodes in #112
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Adding RV128 shift opcodes changed what metadata we emit for SLLI, SRLI,
and SRAI. Thus, downstream tooling that relies on these to connote the
RV64 variants of these instructions is semantically affected.
Fix by reverting SLLI etc. to being the RV64 variants.
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This will reduce the chance that people pick the wrong shamt width.
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Fix pack instruction in unratified/rv_zbpbo
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pack instruction should be imported from zbe -- instead of zbp.
Signed-off-by: Babu P S <11073327+eflaner@users.noreply.github.com>
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Removing import of csrrs and crrci in rv_zpn
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Removing import of csrrs and crrci as the instruction's pseudo opcode for is already included.
Signed-off-by: Babu P S <11073327+eflaner@users.noreply.github.com>
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* Correction of riscv-p-spec opcodes
- Reorganized 'p' into sub-extensions zpn, zpfs & zbpbo
- Some instructions such as insb, smmul has been rearranged according XLEN.
* removed rv_m in rv32_zbpbp + newline additions
Co-authored-by: Babu P S <babu.ps@incoresemi.com>
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support import parse.py from other python script.
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This PR changes opcodes_dir to the REAL path of parse.py. It helps python
scripts which depends on parse.py can be stored in other place, using PYTHONPAT
or sys.path to import from riscv-opcodes/parse.
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That allows for running the script out-of-tree.
Signed-off-by: Florian Zaruba <florian@zaruba.email>
Signed-off-by: Florian Zaruba <florian@zaruba.email>
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The BSD-3-Clause license mentions a copyright notice that has to
be retained while redistributing the source code.
Copy the copyright notice from LICENSE file to the script, so it
get in the generated file.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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This removes the language about patents that was added in #133.
Change copyright holder to RISC-V International.
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* fix extension merge and add name and encoding conflict checking
* fix comments
* uniform code's indentation
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Linux kernel coding style requires the SPDX tag to be placed in
the very first line of the generated file. See kernel file
Documentation/process/license-rules.rst
at chapter 'License identifier syntax', '1. Placement:'.
Move the SPDX tag in the python script.
While there, adjust also the style of the multi-line comment.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Generalize `fence.tso` instruction
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Since `fence.tso' instruction is encoded as a FENCE instruction with
fm=1000, predecessor=RW, and successor=RW (as per the ISA Manual),
`fence.tso' is generalized to have unused rs1 and rd operands (shall
be zero on standard software).
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add field definition for stateen csrs
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Previously the license was a hybrid between the conditions form
BSD-3-Clause-Clear and the disclaimer from MIT-Modern-Variant.
Using a standard license makes it easier to include the generated code
into other open source projects.
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This work is based on Zawrs fast-track extension, version 1.0-rc2.
<https://github.com/riscv/riscv-zawrs/releases/tag/V1.0-rc2>
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This work is based on the latest ISA Manual:
<https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220622-c3b7d92>
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Add CSRs from ratified S* extensions
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cf. <https://github.com/riscv/riscv-time-compare/releases/tag/v0.5.4>
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cf. <https://github.com/riscv/riscv-count-overflow/releases/tag/v0.5.2>
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cf. <https://github.com/riscv/riscv-state-enable/releases/tag/v1.0.0>
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Making a shallow copy of the list prevents updating the final encoding
output when checking for field overlap.
Incorrect:
encoding: 0000000rs2rs2rs2rs2rs2rs1rs1rs1rs1rs1000rdrdrdrdrd0110011
Correct:
encoding: 0000000----------000-----0110011
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