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| author | Andrew Waterman <andrew@sifive.com> | 2023-01-12 13:20:38 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-31 09:27:32 -0800 |
| commit | 33dc95e1a8806bdc21cc1ce95f31a40e972a913b (patch) | |
| tree | 258e3398c09f1d8ed556cdabaad8aca06203301b | |
| parent | 7cfa12ecc41be453ebb5bf9721a41f29d210e7ff (diff) | |
| download | riscv-opcodes-33dc95e1a8806bdc21cc1ce95f31a40e972a913b.zip riscv-opcodes-33dc95e1a8806bdc21cc1ce95f31a40e972a913b.tar.gz riscv-opcodes-33dc95e1a8806bdc21cc1ce95f31a40e972a913b.tar.bz2 | |
Fix backwards incompatibility introduced by RV128 opcodes in #112
Adding RV128 shift opcodes changed what metadata we emit for SLLI, SRLI,
and SRAI. Thus, downstream tooling that relies on these to connote the
RV64 variants of these instructions is semantically affected.
Fix by reverting SLLI etc. to being the RV64 variants.
| -rw-r--r-- | rv32_i | 6 | ||||
| -rw-r--r-- | rv64_i | 6 | ||||
| -rw-r--r-- | unratified/rv128_i | 7 |
3 files changed, 9 insertions, 10 deletions
@@ -1,3 +1,3 @@ -$pseudo_op rv128_i::slli slli rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srli srli rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv128_i::slli slli_rv32 rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv128_i::srli srli_rv32 rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv128_i::srai srai_rv32 rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 @@ -4,9 +4,9 @@ lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 -$pseudo_op rv128_i::slli slli rd rs1 31..26=0 shamtd 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srli srli rd rs1 31..26=0 shamtd 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srai srai rd rs1 31..26=16 shamtd 14..12=5 6..2=0x04 1..0=3 +slli rd rs1 31..26=0 shamtd 14..12=1 6..2=0x04 1..0=3 +srli rd rs1 31..26=0 shamtd 14..12=5 6..2=0x04 1..0=3 +srai rd rs1 31..26=16 shamtd 14..12=5 6..2=0x04 1..0=3 addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3 diff --git a/unratified/rv128_i b/unratified/rv128_i index 05c521e..191d61a 100644 --- a/unratified/rv128_i +++ b/unratified/rv128_i @@ -16,7 +16,6 @@ ldu rd rs1 imm12 14..12=7 6..2=0x00 1..0=3 sq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3 -# RV32 and RV64 versions of these are in opcodes-pseudo -slli rd rs1 31..27=0 shamtq 14..12=1 6..2=0x04 1..0=3 -srli rd rs1 31..27=0 shamtq 14..12=5 6..2=0x04 1..0=3 -srai rd rs1 31..27=8 shamtq 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::slli slli_rv128 rd rs1 31..27=0 shamtq 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srli srli_rv128 rd rs1 31..27=0 shamtq 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srai srai_rv128 rd rs1 31..27=8 shamtq 14..12=5 6..2=0x04 1..0=3 |