Refine rvp (#409)

* rvp: Add P extension

This commit add encodings for P Extension:
https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf
Signed-off-by: 2011eric <201165r1c@gmail.com>

* rvp: rename pmqwacc/mqrwacc

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: pdif has been renamed by pabd

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: fix some missing characters in instructions name

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: ppack has been renamed by ppair

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: add missing instructions

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: remove old grevi

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: convert 56 RV32 scalar instructions to pseudo-instructions of RV64 equivalents

Based on RVP-instrEncodings-019.pdf, converted RV32
scalar instructions that share the same encoding with RV64 packed-word
instructions to pseudo-instructions.

Instructions converted (56 total):
- Pages 4-8: sslai, ssha, sshar (3)
- Page 9: sadd, aadd, saddu, aaddu, ssub, asub, ssubu, asubu (8)
- Page 10: mul.h01, macc.h01, mulu.h01, maccu.h01 (4)
- Page 11: sh1sadd (1)
- Page 12: mul/macc/mulu/maccu/mulsu/maccsu.h00/h11 (12)
- Page 14: mqacc.h01, mqracc.h01 (2)
- Page 15: mseq, mslt, msltu (3)
- Page 16: mulhr, mhacc, mhracc, mulhru, mhaccu, mhraccu, mulh.h0/h1,
  mulhsu.h0/h1, mhacc.h0/h1, mhaccsu.h0/h1, mulhrsu, mhaccsu, mhraccsu,
  mulq, mulqr, mqacc.h00/h11, mqracc.h00/h11 (23)

Also removed packbt/packtb/packt pseudo-instructions that referenced
non-existent rv64_p instructions.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: align indent and add comment by page

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: fix mnemonic typo

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvp: add P-extension scalar pseudo-ops to emitted_pseudo_ops

---------

Signed-off-by: 2011eric <201165r1c@gmail.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Co-authored-by: 2011eric <201165r1c@gmail.com>

1 files changed, 63 insertions, 0 deletions

diff --git a/src/riscv_opcodes/constants.py b/src/riscv_opcodes/constants.py
index fb67d70..757c2f2 100644
--- a/src/riscv_opcodes/constants.py
+++ b/src/riscv_opcodes/constants.py
@@ -8,6 +8,9 @@ overlapping_extensions = {
     "rv_zcmt": {"rv_c_d"},
     "rv_zcmp": {"rv_c_d"},
     "rv_c": {"rv_zcmop"},
+    "rv64_p": {"rv32_p", "rv64_zbp"},
+    "rv32_p": {"rv64_p", "rv_zcmt", "rv_c_d"},
+    "rv_p": {"rv_zbb"},
 }
 
 overlapping_instructions = {
@@ -268,4 +271,64 @@ emitted_pseudo_ops = [
     "zext.h.rv32",
     "rev8.h.rv32",
     "rori.rv32",
+    # P-extension scalar pseudo-ops (rv_p / rv32_p / rv64_p)
+    "aadd",
+    "aaddu",
+    "asub",
+    "asubu",
+    "macc_h00",
+    "macc_h01",
+    "macc_h11",
+    "maccsu_h00",
+    "maccsu_h11",
+    "maccu_h00",
+    "maccu_h01",
+    "maccu_h11",
+    "mhacc",
+    "mhacc_h0",
+    "mhacc_h1",
+    "mhaccsu",
+    "mhaccsu_h0",
+    "mhaccsu_h1",
+    "mhaccu",
+    "mhracc",
+    "mhraccsu",
+    "mhraccu",
+    "mqacc_h00",
+    "mqacc_h01",
+    "mqacc_h11",
+    "mqracc_h00",
+    "mqracc_h01",
+    "mqracc_h11",
+    "mseq",
+    "mslt",
+    "msltu",
+    "mul_h00",
+    "mul_h01",
+    "mul_h11",
+    "mulh_h0",
+    "mulh_h1",
+    "mulhr",
+    "mulhrsu",
+    "mulhru",
+    "mulhsu_h0",
+    "mulhsu_h1",
+    "mulq",
+    "mulqr",
+    "mulsu_h00",
+    "mulsu_h11",
+    "mulu_h00",
+    "mulu_h01",
+    "mulu_h11",
+    "sadd",
+    "saddu",
+    "sati_rv32",
+    "ssh1sadd",
+    "srari_rv32",
+    "ssha",
+    "sshar",
+    "sslai",
+    "ssub",
+    "ssubu",
+    "usati_rv32",
 ]