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author | Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com> | 2024-06-04 16:20:56 -0500 |
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committer | GitHub <noreply@github.com> | 2024-06-04 14:20:56 -0700 |
commit | ea2fec121a59136b0dada11743bf6c545c996c65 (patch) | |
tree | 831cd9c45af37208cf932866c341dd6cd50fff6a /csrs.csv | |
parent | 5181d13bef845edfb511e3132a7e661090e3204b (diff) | |
download | riscv-opcodes-ea2fec121a59136b0dada11743bf6c545c996c65.zip riscv-opcodes-ea2fec121a59136b0dada11743bf6c545c996c65.tar.gz riscv-opcodes-ea2fec121a59136b0dada11743bf6c545c996c65.tar.bz2 |
Add unratified Smctr/Ssctr instructions and CSRs (#252)
Diffstat (limited to 'csrs.csv')
-rw-r--r-- | csrs.csv | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -61,6 +61,8 @@ 0x143, "stval" 0x144, "sip" 0x14D, "stimecmp" +0x14E, "sctrctl" +0x14F, "sctrstatus" 0x150, "siselect" 0x151, "sireg" 0x152, "sireg2" @@ -69,6 +71,7 @@ 0x156, "sireg5" 0x157, "sireg6" 0x15C, "stopei" +0x15F, "sctrdepth" 0x180, "satp" 0x181, "srmcfg" 0x5A8, "scontext" @@ -81,6 +84,7 @@ 0x243, "vstval" 0x244, "vsip" 0x24D, "vstimecmp" +0x24E, "vsctrctl" 0x250, "vsiselect" 0x251, "vsireg" 0x252, "vsireg2" @@ -153,6 +157,7 @@ 0x344, "mip" 0x34a, "mtinst" 0x34b, "mtval2" +0x34E, "mctrctl" 0x350, "miselect" 0x351, "mireg" 0x352, "mireg2" |