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| author | Ved Shanbhogue <ved@rivosinc.com> | 2023-12-23 11:00:51 -0700 |
|---|---|---|
| committer | Ved Shanbhogue <ved@rivosinc.com> | 2023-12-23 11:00:51 -0700 |
| commit | d5f2867929385ff81d92a411cde685a6bbd40a65 (patch) | |
| tree | 1b11af3255fc97cd01ef15602f4e70cab2afd2c7 | |
| parent | 61d2ef45dcb4a276a1e69643880cb75a9ca5ba79 (diff) | |
| download | riscv-opcodes-d5f2867929385ff81d92a411cde685a6bbd40a65.zip riscv-opcodes-d5f2867929385ff81d92a411cde685a6bbd40a65.tar.gz riscv-opcodes-d5f2867929385ff81d92a411cde685a6bbd40a65.tar.bz2 | |
add srmcfg CSR
| -rw-r--r-- | csrs.csv | 1 | ||||
| -rw-r--r-- | encoding.h | 4 |
2 files changed, 5 insertions, 0 deletions
@@ -70,6 +70,7 @@ 0x157, "sireg6" 0x15C, "stopei" 0x180, "satp" +0x181, "srmcfg" 0x5A8, "scontext" 0x200, "vsstatus" 0x204, "vsie" @@ -330,6 +330,10 @@ #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) +/* srmcfg CSR fields */ +#define SRMCFG_RCID 0x00000FFF +#define SRMCFG_MCID 0x0FFF0000 + #ifdef __riscv #if __riscv_xlen == 64 |