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==========================================================================
RISC-V ISA Simulator
==========================================================================
# Author : Andrew Waterman, Yunsup Lee
# Date : June 19, 2011
# Version : (under version control)
The RISC-V ISA Simulator implements a functional model of one or more
RISC-V processors.
--------------------------------------------------------------------------
Build Steps
--------------------------------------------------------------------------
We assume that the RISCV environment variable is set to the RISC-V tools
install path, and that the riscv-fesvr package is installed there.
% mkdir build
% cd build
% ../configure --prefix=$RISCV --with-fesvr=$RISCV
% make
% [sudo] make install
--------------------------------------------------------------------------
Compiling and Running a Simple C Program
--------------------------------------------------------------------------
Install spike (see Build Steps), riscv-gcc, and riscv-pk.
Write a short C program and name it hello.c. Then, compile it into a RISC-V
ELF binary named hello:
% riscv-gcc -o hello hello.c
Now you can simulate the program atop the proxy kernel:
% spike pk hello
--------------------------------------------------------------------------
Simulating a New Instruction
--------------------------------------------------------------------------
Adding an instruction to the simulator requires two steps:
1. Describe the instruction's functional behavior in the file
riscv/insns/<new_instruction_name>.h. Examine other instructions
in that directory as a starting point.
2. Add the opcode and opcode mask to riscv/opcodes.h. Alternatively,
add it to the riscv-opcodes package, and it will do so for you:
% cd ../riscv-opcodes
% vi opcodes // add a line for the new instruction
% make install
3. Rebuild the simulator.
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