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AgeCommit message (Expand)AuthorFilesLines
2014-02-14Renumber uarch CSRs into custom CSR spaceAndrew Waterman1-16/+16
2014-02-13Fix I$ simulator not making forward progressAndrew Waterman2-21/+17
2014-02-12Fix commit log when !debugAndrew Waterman1-25/+15
2014-02-10Revert to old AUIPC definitionAndrew Waterman1-1/+1
2014-02-07Clear EVEC LSBs, which kindly prevents a segfaultAndrew Waterman1-2/+2
2014-02-06commit missing definitions for uarch countersYunsup Lee1-0/+56
2014-01-31Fix linking on DarwinAndrew Waterman1-2/+0
2014-01-28Force extension loaders to be linked inAndrew Waterman1-6/+0
2014-01-26Enable runtime loading of dynamic library with --extlibAndrew Waterman1-2/+0
2014-01-26Eliminate hwacha <-> riscv circular dependenceAndrew Waterman6-615/+0
2014-01-25Merge softfloat_riscv into softfloatAndrew Waterman1-1/+0
2014-01-24Require libdl for dynamic linking at runtimeAndrew Waterman1-0/+2
2014-01-24Disassemble amoxorAndrew Waterman1-0/+2
2014-01-24Build and use shared libraries onlyAndrew Waterman1-2/+2
2014-01-24Build and use shared librariesAndrew Waterman1-2/+2
2014-01-24Handle CSR permissions correctlyAndrew Waterman2-6/+10
2014-01-21Use auto-generated trap cause numbersAndrew Waterman2-26/+52
2014-01-20Merge branch 'confprec'Quan Nguyen33-0/+0
2014-01-16Initialize tohost and fromhost to zeroAndrew Waterman1-2/+5
2014-01-13Improve performance for branchy codeAndrew Waterman13-84/+130
2013-12-17Speed things up quite a bitAndrew Waterman6-78/+117
2013-12-09New RDCYCLE encodingAndrew Waterman9-38/+39
2013-11-25Update to new privileged ISAAndrew Waterman29-399/+785
2013-11-24Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEADQuan Nguyen5-2/+6
2013-11-21fix slli/slliw encoding bugYunsup Lee1-2/+2
2013-11-05add accelerator disabled causeYunsup Lee1-0/+1
2013-11-05correctly trap when SR_EA is disabledYunsup Lee3-0/+3
2013-11-04Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into confprecAlbert Ou13-147/+131
2013-10-28Pass target machine's return code back to OSAndrew Waterman3-3/+4
2013-10-27Add missing fcvt opcodes through riscv-opcodesQuan Nguyen1-37/+4
2013-10-18clean up SR_EA, the enable accelerator bit in status regYunsup Lee2-5/+4
2013-10-18refactor disassembler, and add hwacha disassemblerYunsup Lee11-139/+123
2013-10-17Add empty opcode header files for half-precisionQuan Nguyen34-4/+37
2013-10-17add hwacha exception supportYunsup Lee2-14/+1
2013-10-17fix custom-1 rocc encodingYunsup Lee1-1/+1
2013-10-16use reset virtual methodYunsup Lee1-1/+1
2013-10-16fix missing null check when there's no extensionYunsup Lee1-1/+2
2013-10-16revamp hwacha; now runs in physical modeYunsup Lee8-7/+9
2013-10-15Propogate the reset call to the extensions as well. Add reset function to ext...Stephen Twigg3-1/+8
2013-10-15Fix bug where xs2 was not being properly respected.Stephen Twigg1-1/+1
2013-09-27Added commit logging (--enable-commitlog). Also fixed disasm bug.Christopher Celio4-6/+54
2013-09-27Use WRITE_RD/WRITE_FRD macros to write registersAndrew Waterman141-185/+167
2013-09-23fixes compile bug for not being able to find std::logic_errorScott Beamer1-0/+1
2013-09-23Fix Scott's deadlockAndrew Waterman3-7/+11
2013-09-22Adjust rocc_inst_t to properly extract fields due to the new ISA encoding.Stephen Twigg1-3/+3
2013-09-21Update ISA encoding and AUIPC semanticsAndrew Waterman3-168/+170
2013-09-15Add helper disassembly programAndrew Waterman2-0/+42
2013-09-15ISA changesAndrew Waterman1-2/+2
2013-09-11Add AMOXORAndrew Waterman3-16/+25
2013-09-11Implement zany immediatesAndrew Waterman39-459/+233
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