index
:
rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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riscv
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Author
Files
Lines
2014-04-03
Merge branch 'tm'
Stephen Twigg
1
-3
/
+3
2014-04-03
Sync encoding in opcodes
Stephen Twigg
1
-3
/
+15
2014-03-18
Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
Andrew Waterman
8
-11
/
+29
2014-03-15
speed up compilation a bit
Andrew Waterman
2
-2
/
+2
2014-03-11
New FP encoding
Andrew Waterman
1
-42
/
+42
2014-03-06
Add fclass.{s|d} instructions
Andrew Waterman
3
-0
/
+10
2014-02-25
add extensions to riscv-dis for better disassembly
Yunsup Lee
1
-1
/
+16
2014-02-14
Renumber uarch CSRs into custom CSR space
Andrew Waterman
1
-16
/
+16
2014-02-13
Fix I$ simulator not making forward progress
Andrew Waterman
2
-21
/
+17
2014-02-12
Fix commit log when !debug
Andrew Waterman
1
-25
/
+15
2014-02-10
Revert to old AUIPC definition
Andrew Waterman
1
-1
/
+1
2014-02-07
Clear EVEC LSBs, which kindly prevents a segfault
Andrew Waterman
1
-2
/
+2
2014-02-06
commit missing definitions for uarch counters
Yunsup Lee
1
-0
/
+56
2014-01-31
Fix linking on Darwin
Andrew Waterman
1
-2
/
+0
2014-01-28
Force extension loaders to be linked in
Andrew Waterman
1
-6
/
+0
2014-01-26
Enable runtime loading of dynamic library with --extlib
Andrew Waterman
1
-2
/
+0
2014-01-26
Eliminate hwacha <-> riscv circular dependence
Andrew Waterman
6
-615
/
+0
2014-01-25
Merge softfloat_riscv into softfloat
Andrew Waterman
1
-1
/
+0
2014-01-24
Require libdl for dynamic linking at runtime
Andrew Waterman
1
-0
/
+2
2014-01-24
Disassemble amoxor
Andrew Waterman
1
-0
/
+2
2014-01-24
Build and use shared libraries only
Andrew Waterman
1
-2
/
+2
2014-01-24
Build and use shared libraries
Andrew Waterman
1
-2
/
+2
2014-01-24
Handle CSR permissions correctly
Andrew Waterman
2
-6
/
+10
2014-01-21
Use auto-generated trap cause numbers
Andrew Waterman
2
-26
/
+52
2014-01-20
Merge branch 'confprec'
Quan Nguyen
33
-0
/
+0
2014-01-16
Initialize tohost and fromhost to zero
Andrew Waterman
1
-2
/
+5
2014-01-13
Improve performance for branchy code
Andrew Waterman
13
-84
/
+130
2013-12-17
Speed things up quite a bit
Andrew Waterman
6
-78
/
+117
2013-12-09
New RDCYCLE encoding
Andrew Waterman
9
-38
/
+39
2013-11-25
Update to new privileged ISA
Andrew Waterman
29
-399
/
+785
2013-11-24
Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEAD
Quan Nguyen
5
-2
/
+6
2013-11-21
fix slli/slliw encoding bug
Yunsup Lee
1
-2
/
+2
2013-11-05
add accelerator disabled cause
Yunsup Lee
1
-0
/
+1
2013-11-05
correctly trap when SR_EA is disabled
Yunsup Lee
3
-0
/
+3
2013-11-04
Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into confprec
Albert Ou
13
-147
/
+131
2013-10-28
Pass target machine's return code back to OS
Andrew Waterman
3
-3
/
+4
2013-10-27
Add missing fcvt opcodes through riscv-opcodes
Quan Nguyen
1
-37
/
+4
2013-10-18
clean up SR_EA, the enable accelerator bit in status reg
Yunsup Lee
2
-5
/
+4
2013-10-18
refactor disassembler, and add hwacha disassembler
Yunsup Lee
11
-139
/
+123
2013-10-17
Add empty opcode header files for half-precision
Quan Nguyen
34
-4
/
+37
2013-10-17
add hwacha exception support
Yunsup Lee
2
-14
/
+1
2013-10-17
fix custom-1 rocc encoding
Yunsup Lee
1
-1
/
+1
2013-10-16
use reset virtual method
Yunsup Lee
1
-1
/
+1
2013-10-16
fix missing null check when there's no extension
Yunsup Lee
1
-1
/
+2
2013-10-16
revamp hwacha; now runs in physical mode
Yunsup Lee
8
-7
/
+9
2013-10-15
Propogate the reset call to the extensions as well. Add reset function to ext...
Stephen Twigg
3
-1
/
+8
2013-10-15
Fix bug where xs2 was not being properly respected.
Stephen Twigg
1
-1
/
+1
2013-09-27
Added commit logging (--enable-commitlog). Also fixed disasm bug.
Christopher Celio
4
-6
/
+54
2013-09-27
Use WRITE_RD/WRITE_FRD macros to write registers
Andrew Waterman
141
-185
/
+167
2013-09-23
fixes compile bug for not being able to find std::logic_error
Scott Beamer
1
-0
/
+1
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