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rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
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tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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riscv
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sim.h
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Author
Files
Lines
2017-11-15
Support for non-contiguous hartids
Gleb Gagarin
1
-1
/
+1
2017-05-16
Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10
Palmer Dabbelt
1
-5
/
+8
2017-05-01
Set default entry point from ELF
Andrew Waterman
1
-2
/
+2
2017-04-30
Add option to set start pc
Andrew Waterman
1
-1
/
+2
2017-04-30
Support more flexible main memory allocation
Andrew Waterman
1
-7
/
+4
2017-04-30
Store both host & target address in soft TLB
Andrew Waterman
1
-2
/
+1
2017-04-17
Merge remote-tracking branch 'origin/priv-1.10' into HEAD
Megan Wachs
1
-5
/
+7
2017-04-10
Implement new FP encoding
Andrew Waterman
1
-1
/
+2
2017-03-22
riscv: replace rtc device with a real clint implementation
Wesley W. Terpstra
1
-1
/
+1
2017-03-21
configstring: rename variables to dts
Wesley W. Terpstra
1
-3
/
+3
2017-03-21
sim: define emulated CPU clock rate to be 1GHz
Wesley W. Terpstra
1
-0
/
+1
2017-02-10
Entering debug mode now jumps to "dynamic rom"
Tim Newsome
1
-0
/
+1
2017-02-07
OpenOCD does a dmi read and gets dummy value back.
Tim Newsome
1
-1
/
+2
2017-02-03
OpenOCD connects, and sends some data that we receive.
Tim Newsome
1
-4
/
+5
2016-06-22
Remove legacy HTIF; implement HTIF directly
Andrew Waterman
1
-13
/
+20
2016-05-23
Have Debug memory kind of working again.
Tim Newsome
1
-3
/
+0
2016-05-23
Add debug_module bus device.
Tim Newsome
1
-6
/
+6
2016-05-23
ROM -> RAM -> ROM, waiting for debug int.
Tim Newsome
1
-0
/
+5
2016-05-23
Add -H to start halted.
Tim Newsome
1
-1
/
+1
2016-05-23
gdb can now read spike memory.
Tim Newsome
1
-0
/
+1
2016-05-23
Listen on a socket for gdb to connect to.
Tim Newsome
1
-0
/
+3
2016-05-02
Remove tohost/fromhost registers
Andrew Waterman
1
-2
/
+0
2016-04-30
Remove SCRs; add padding after config string
Andrew Waterman
1
-7
/
+3
2016-04-29
Move much closer to new platform-M memory map
Andrew Waterman
1
-3
/
+9
2016-04-28
Add --dump-config-string flag
Andrew Waterman
1
-0
/
+1
2016-04-28
Remove MTIME[CMP]; add RTC device
Andrew Waterman
1
-1
/
+2
2016-03-02
Use RV config string rather than FDT
Andrew Waterman
1
-2
/
+2
2015-11-12
Generate device tree for target machine
Andrew Waterman
1
-3
/
+4
2015-09-24
Refactor memory access code; add MMIO support
Andrew Waterman
1
-0
/
+5
2015-08-06
Add an option (-l) to display a log of execution in non-interactive mode.
Prashanth Mundkur
1
-0
/
+2
2015-06-05
add an interactive "pc" command
Mike Frysinger
1
-0
/
+1
2015-06-05
unify interactive core processing
Mike Frysinger
1
-0
/
+1
2015-06-04
add a help screen to interactive mode
Mike Frysinger
1
-0
/
+1
2015-05-31
Use single, shared real-time counter
Andrew Waterman
1
-0
/
+2
2015-04-03
Support setting ISA/subsets with --isa flag
Andrew Waterman
1
-1
/
+3
2014-08-15
Added PC histogram option.
Christopher Celio
1
-0
/
+2
2014-01-13
Improve performance for branchy code
Andrew Waterman
1
-1
/
+2
2013-11-25
Update to new privileged ISA
Andrew Waterman
1
-1
/
+1
2013-10-28
Pass target machine's return code back to OS
Andrew Waterman
1
-1
/
+1
2013-10-18
refactor disassembler, and add hwacha disassembler
Yunsup Lee
1
-2
/
+3
2013-08-11
Instructions are no longer member functions
Andrew Waterman
1
-1
/
+1
2013-07-26
Generate instruction decoder dynamically
Andrew Waterman
1
-1
/
+1
2013-07-22
Add xspike program
Andrew Waterman
1
-0
/
+2
2013-07-12
Eliminate infinite loop in debug mode
Andrew Waterman
1
-0
/
+1
2013-07-12
Exit cleanly from debug console
Andrew Waterman
1
-6
/
+6
2013-04-23
destroy htif on simulator termination
Andrew Waterman
1
-1
/
+2
2013-03-29
add load-reserved/store-conditional instructions
Andrew Waterman
1
-10
/
+5
2013-03-25
add BSD license
Andrew Waterman
1
-0
/
+2
2013-02-13
add I$/D$/L2$ simulators
Andrew Waterman
1
-0
/
+1
2013-01-25
change htif to link against libfesvr
Andrew Waterman
1
-9
/
+7
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