aboutsummaryrefslogtreecommitdiff
path: root/riscv/sim.cc
AgeCommit message (Expand)AuthorFilesLines
2019-10-28Implement support for big-endian hostsMarcus Comstedt1-2/+5
2019-10-16Enforce 2^56-bit physical address limitAndrew Waterman1-2/+9
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-1/+10
2019-07-22Implement MMIO device plugins.Aaron Jones1-4/+8
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao1-4/+4
2019-05-14Clean up debug module options. (#299)Tim Newsome1-7/+3
2019-04-04Add --debug-no-abstract-csr (#267)Tim Newsome1-2/+4
2019-04-02Implement debug hasel support (#287)Tim Newsome1-2/+2
2018-12-13Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome1-2/+4
2018-08-23Add --disable-dtb option to suppress writing the DTB to memoryAndrew Waterman1-2/+3
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-1/+1
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur1-142/+2
2018-03-16Implement debug havereset bitsTim Newsome1-0/+5
2018-03-07Merge pull request #177 from riscv/debug_authTim Newsome1-2/+3
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-3/+3
2018-02-27Add debug module authentication.Tim Newsome1-2/+3
2018-02-01Add --debug-sba optionTim Newsome1-2/+3
2018-01-18Support debug system bus access.Tim Newsome1-4/+3
2017-12-11Make progbuf a run-time option.Tim Newsome1-2/+4
2017-11-15Merge pull request #156 from p12nGH/noncontiguous_hartsAndrew Waterman1-3/+14
2017-11-15Support for non-contiguous hartidsGleb Gagarin1-3/+14
2017-11-03Put HTIF in the device treePalmer Dabbelt1-0/+3
2017-06-14Support 64-bit start PCs in reset vector.Tim Newsome1-12/+10
2017-05-16Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10Palmer Dabbelt1-6/+6
2017-05-01Fix segfault when accessing bad memory addressesAndrew Waterman1-2/+3
2017-05-01Set default entry point from ELFAndrew Waterman1-2/+6
2017-04-30Add option to set start pcAndrew Waterman1-8/+18
2017-04-30Support more flexible main memory allocationAndrew Waterman1-24/+21
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-48/+156
2017-03-30fdt: move interrupt controller into its own nodeWesley W. Terpstra1-4/+7
2017-03-24Default to 2 GiB of memoryAndrew Waterman1-1/+1
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-13/+11
2017-03-21sim: declare cores as interrupt-controllers for clintWesley W. Terpstra1-0/+2
2017-03-21bootrom: set a0 to hartid and a1 to dtb before bootWesley W. Terpstra1-7/+7
2017-03-21configstring: rename variables to dtsWesley W. Terpstra1-4/+4
2017-03-21bootrom: include compiled dtbWesley W. Terpstra1-1/+87
2017-03-21sim: create DTS instead of config stringWesley W. Terpstra1-26/+45
2017-02-13Abstract register read mostly working.Tim Newsome1-1/+1
2017-02-10Implement hartstatus field.Tim Newsome1-1/+1
2017-02-03OpenOCD connects, and sends some data that we receive.Tim Newsome1-4/+4
2016-12-16Use correct format codes for reg_t and size_tStefan O'Rear1-2/+2
2016-08-29Fix indent.Tim Newsome1-1/+1
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-14/+39
2016-05-23Make -H halt the core right out of reset.Tim Newsome1-3/+1
2016-05-23Have Debug memory kind of working again.Tim Newsome1-7/+2
2016-05-23Add debug_module bus device.Tim Newsome1-7/+8
2016-05-23Make sure to translate Debug RAM addresses also.Tim Newsome1-2/+3
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-1/+8
2016-05-23Gutting direct-access gdb.Tim Newsome1-1/+1
2016-05-23Add --gdb-portTim Newsome1-1/+1