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2018-04-04Allow querying the mmu configuration chosen during the build. (#191)Prashanth Mundkur1-0/+18
2018-03-06Narrow the interface used by the processors and memory to the top-level ↵Prashanth Mundkur1-2/+2
simulator/htif. This allows the implementation of an alternative top-level simulator class.
2018-02-21Don't allow 32-bit instructions to take up multiple slots in I$Andrew Waterman1-1/+2
I$ indices now maintain a 1:N relationship with PCs. This is somewhat faster and also simpler.
2017-11-27Rename badaddr to tvalAndrew Waterman1-2/+2
2017-11-27Rename sptbr to satpAndrew Waterman1-10/+10
2017-09-28Implement Q extensionAndrew Waterman1-0/+19
2017-04-30Store both host & target address in soft TLBAndrew Waterman1-20/+29
2017-04-05Add --enable-misaligned option for misaligned ld/st supportAndrew Waterman1-4/+26
Resolves #93
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-0/+3
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman1-0/+31
https://github.com/riscv/riscv-isa-manual/issues/4 Also, refactor gdbserver code to not duplicate VM decoding logic.
2016-11-13Fix 32-bit host portability bugAndrew Waterman1-1/+1
2016-11-10AMOs should always return store faults, not load faultsAndrew Waterman1-0/+20
This commit also factors out the common AMO code into mmu_t.
2016-09-02Support triggers on TLB misses.Tim Newsome1-0/+3
2016-09-01Theoretically support trigger timing.Tim Newsome1-0/+3
2016-08-22Implement address and data triggers.Tim Newsome1-0/+55
So far I only have testcases for instruction and data address. Not implemented is the mechanism that lets the debugger prevent a user program from using triggers at all. I'll be adding that soonish. The critical path is unchanged, but my experimenting shows the simulation is slowed down about 8% by this code. Reducing the size of trigger_match() (which is never called during my benchmark) fixes that, but making it not be inlined has no effect. I suspect the slowdown comes from cache alignment or something similar, and on a different CPU or after more code changes the speed will come back.
2016-07-06Update to new PTE formatAndrew Waterman1-1/+1
2016-06-22Don't use I$ in debug modeAndrew Waterman1-3/+4
This avoids the need for fence.i.
2016-05-23Use fence.i in Debug ROM.Tim Newsome1-1/+0
This replaces a hack that just disabled all of the icache.
2016-05-23gdb can attach and read the PC:Tim Newsome1-0/+1
(gdb) target remote localhost:1234 Remote debugging using localhost:1234 0x0000000000010178 in fib (n=0) at waste.c:1 1 unsigned int fib(unsigned int n) { (gdb)
2016-05-23Add debug_module bus device.Tim Newsome1-2/+4
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-10/+6
Reset vector is at 0x1000; below that is reserved for debug Memory is at 0x80000000
2016-03-02implement PUM functionalityAndrew Waterman1-1/+1
2015-09-24Refactor memory access code; add MMIO supportAndrew Waterman1-36/+38
Of course, it doesn't do anything yet.
2015-09-24Use enum instead of two bools to denote memory access typeAndrew Waterman1-19/+21
2015-09-08Improve instruction fetchAndrew Waterman1-15/+15
- Performance for variable-length instructions is much better - Refill is simpler and faster - Support for instructions with overlapping opcodes (e.g. C.ADD + C.JALR)
2015-07-10fix clang compile errorScott Beamer1-0/+1
2015-04-25Fix I$ simulator hit countAndrew Waterman1-4/+5
Also, improve performance by allowing the soft-ITLB to refill.
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-7/+2
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2015-03-30Implement RVC draftAndrew Waterman1-12/+11
2015-03-26New virtual memory implementation (Sv39)Andrew Waterman1-4/+3
2015-03-14Don't set dirty/referenced bits w/o permissionAndrew Waterman1-1/+1
2015-03-12Implement PTE referenced/dirty bitsAndrew Waterman1-2/+2
2015-01-02Require 4-byte instruction alignment until RVC is reimplementedAndrew Waterman1-1/+2
2015-01-02On misaligned fetch, set EPC to target, not branch itselfAndrew Waterman1-1/+3
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-3/+4
In particular, precompiled headers ideally won't depend on any.
2014-12-04Support 2/4/6/8-byte instructionsAndrew Waterman1-13/+32
Most of the complexity is in instruction address translation, since instructions may span page boundaries.
2014-02-13Fix I$ simulator not making forward progressAndrew Waterman1-5/+5
2014-01-13Improve performance for branchy codeAndrew Waterman1-35/+39
We now use a heavily unrolled loop as the software I$, which allows the host machine's branch target prediction to associate target PCs with unique-ish host PCs.
2013-12-17Speed things up quite a bitAndrew Waterman1-31/+40
2013-09-11Implement zany immediatesAndrew Waterman1-8/+11
2013-08-11Instructions are no longer member functionsAndrew Waterman1-25/+2
2013-07-28Don't flush TLB on PTBR writes (only FATC)Andrew Waterman1-1/+1
2013-07-26New supervisor modeAndrew Waterman1-17/+3
2013-07-26Remove more vector stuffAndrew Waterman1-3/+0
2013-07-26Rip out RVC for nowAndrew Waterman1-42/+17
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-22/+18
This will make it easier for accelerators to add instructions.
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-2/+13
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25truncate effective addresses in rv32Andrew Waterman1-11/+4
also, employ a more efficient instruction dispatch based upon rv32 mode.
2013-02-15don't store host pointers in soft TLBAndrew Waterman1-15/+18
this reduces performance by epsilon, but it simplifies hooking into the MMU
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