| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2023-05-18 | Call stash_privilege more selectivelyrivosinc-etrigger_fix_exception_match | Andrew Waterman | 1 | -0/+1 | |
| 2022-11-21 | When resuming from debug mode, clear mstatus.MPRV if the new privilege mode ↵ | YenHaoChen | 1 | -0/+2 | |
| is less than M-mode (#1149) | |||||
| 2021-09-26 | Convert dcsr to csr_t | Scott Johnson | 1 | -2/+2 | |
| 2021-09-26 | Convert dpc to csr_t | Scott Johnson | 1 | -1/+1 | |
| 2019-07-12 | DRET should not be legal in M-mode | Andrew Waterman | 1 | -1/+1 | |
| 2019-07-12 | Add debug_mode state bit, rather than overloading dcsr.cause | Andrew Waterman | 1 | -1/+1 | |
| In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec. | |||||
| 2016-08-17 | Allow mstatus.MPP to store bad values; instead, validate on MRET | Andrew Waterman | 1 | -4/+1 | |
| Either approach is legal, but this more closely matches Rocket. | |||||
| 2016-07-28 | Add support for virtual priv register. (#59) | Tim Newsome | 1 | -1/+4 | |
| Users can use this register to inspect and change the privilege level of the core. It doesn't make any assumptions about the actual underlying debug mechanism (as opposed to having the user change DCSR directly, which may not exist in all debug implementations). | |||||
| 2016-05-23 | Single step appears to work. | Tim Newsome | 1 | -0/+3 | |
| 2016-05-23 | Add dret. | Tim Newsome | 1 | -0/+6 | |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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