| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2014-01-24 | Disassemble amoxor | Andrew Waterman | 1 | -0/+2 |
| 2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 1 | -8/+8 |
| 2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -21/+27 |
| 2013-10-18 | refactor disassembler, and add hwacha disassembler | Yunsup Lee | 1 | -110/+13 |
| 2013-09-27 | Added commit logging (--enable-commitlog). Also fixed disasm bug. | Christopher Celio | 1 | -6/+6 |
| 2013-09-11 | Implement zany immediates | Andrew Waterman | 1 | -309/+138 |
| 2013-09-10 | Add rd field to JAL; drop J | Andrew Waterman | 1 | -3/+2 |
| 2013-08-08 | Rename MTFSR/MFFSR to FSSR/FRSR | Andrew Waterman | 1 | -3/+3 |
| 2013-07-26 | Rename MFTX/MXTF to FMV | Andrew Waterman | 1 | -4/+4 |
| 2013-07-26 | Rip out Hwacha for now | Andrew Waterman | 1 | -70/+0 |
| 2013-07-26 | Generate instruction decoder dynamically | Andrew Waterman | 1 | -2/+2 |
| 2013-07-25 | Remove JALR static hints | Andrew Waterman | 1 | -7/+4 |
| 2013-04-19 | update abi register names | Andrew Waterman | 1 | -8/+8 |
| 2013-04-17 | add AUIPC insn; remove RDNPC insn | Andrew Waterman | 1 | -1/+1 |
| 2013-03-29 | add load-reserved/store-conditional instructions | Andrew Waterman | 1 | -0/+5 |
| 2013-03-25 | add BSD license | Andrew Waterman | 1 | -0/+2 |
| 2013-01-25 | change htif to link against libfesvr | Andrew Waterman | 1 | -16/+10 |
| 2012-03-24 | new supervisor mode | Andrew Waterman | 1 | -6/+6 |
| 2012-03-24 | add disasm functions for vector | Yunsup Lee | 1 | -0/+156 |
| 2012-02-13 | fix sltu disassembly | Andrew Waterman | 1 | -1/+1 |
| 2012-01-11 | fix compilation for gcc 4.6.1 | Andrew Waterman | 1 | -0/+16 |
| 2011-12-10 | fix the fpr abi names | Yunsup Lee | 1 | -2/+2 |
| 2011-11-11 | Remove dependence on binutils | Your Name | 1 | -0/+566 |
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index : rocket-tools/riscv-isa-sim.git | |
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