index
:
rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
debug_rom
Age
Commit message (
Expand
)
Author
Files
Lines
2018-03-06
Fix install of a missed header from debug_rom.
Prashanth Mundkur
2
-3
/
+3
2018-03-06
Fix a missed header file in the softfloat include install.
Prashanth Mundkur
1
-23
/
+0
2017-06-08
`make clean && make` works again in debug_rom
Tim Newsome
2
-2
/
+2
2017-04-18
debug: Add fence and fence.i to ensure Debug RAM is ready.
Megan Wachs
2
-26
/
+14
2017-04-18
debug: Checkpoint which somewhat works with OpenOCD v13, but still has some b...
Megan Wachs
1
-0
/
+1
2017-04-17
debug: move the debug_rom defines to a seperate file
Megan Wachs
2
-5
/
+15
2017-04-17
debug: Use more unique debug ROM names
Megan Wachs
3
-16
/
+32
2017-04-17
debug: Use a more practical debug ROM
Megan Wachs
4
-161
/
+83
2016-09-02
Rebuild debug ROM because CSR encoding changed.
Tim Newsome
1
-2
/
+2
2016-06-22
Parameterize debug ROM contents on XLEN
Andrew Waterman
4
-28
/
+81
2016-06-22
Remove fence.i from debug ROM
Andrew Waterman
1
-1
/
+0
2016-06-09
Fix 2 bugs in Debug ROM: (#52)
Tim Newsome
2
-10
/
+12
2016-06-03
DCSR cause was moved, bug debug ROM wasn't updated
Tim Newsome
2
-3
/
+3
2016-06-01
Add gitignore
Andrew Waterman
1
-0
/
+2
2016-06-01
Move sethaltnot and cleardebint.
Tim Newsome
2
-4
/
+4
2016-05-24
New encoding.h for new CSR addresses.
Tim Newsome
2
-5
/
+5
2016-05-24
Move cleardebint, per spec.
Tim Newsome
2
-3
/
+3
2016-05-23
Change DCSR bits to match spec.
Tim Newsome
2
-22
/
+14
2016-05-23
Move debug rom link map to the right place.
Tim Newsome
2
-2
/
+2
2016-05-23
Use fence.i in Debug ROM.
Tim Newsome
2
-9
/
+10
2016-05-23
Add dret.
Tim Newsome
2
-3
/
+2
2016-05-23
Implement single memory read access.
Tim Newsome
2
-24
/
+29
2016-05-23
Exceptions in Debug Mode, stay in Debug Mode.
Tim Newsome
2
-16
/
+28
2016-05-23
Have Debug memory kind of working again.
Tim Newsome
2
-14
/
+13
2016-05-23
Fix race using fence.
Tim Newsome
2
-21
/
+16
2016-05-23
Refactor how we track in-progress operations.
Tim Newsome
1
-0
/
+1
2016-05-23
processor_t unfriends gdbserver_t.
Tim Newsome
2
-2
/
+2
2016-05-23
Add debug_module bus device.
Tim Newsome
3
-15
/
+14
2016-05-23
ROM -> RAM -> ROM, waiting for debug int.
Tim Newsome
2
-2
/
+2
2016-05-23
Jump to the correct (temporary) Debug RAM address.
Tim Newsome
2
-6
/
+7
2016-05-23
Clean up how Debug ROM is included.
Tim Newsome
4
-0
/
+154
2016-05-23
Can jump to and execute Debug ROM.
Tim Newsome
4
-154
/
+0
2016-05-23
Check in compiled debug ROM.
Tim Newsome
2
-3
/
+24
2016-05-23
Add debug rom code.
Tim Newsome
3
-0
/
+133