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2019-03-31Merge pull request #291 from riscv/do-versioningv1.0.0Andrew Waterman4-7/+41
Version 1.0.0
2019-03-31Build fesvr as -fPIC to improve compatibility with old usesAndrew Waterman2-2/+4
2019-03-31Version 1.0.0Andrew Waterman4-7/+41
2019-03-31Add fesvr; only globally install fesvr headers/libsstatic-linkAndrew Waterman41-232/+6512
2019-03-30Don't install generated headersAndrew Waterman1-1/+1
2019-03-30Statically link the built-in librariesAndrew Waterman1-11/+10
Several people have raised the concern that dynamically linking the built-in components of Spike causes more headaches than it's worth. IIRC, the only reason we did this is to better support the `--extension=libfoo.so` feature.
2019-03-30RV32Q is not invalidAndrew Waterman1-3/+0
https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f#diff-2a8fece1cbcdf623cafbce866ea7d4d0R7
2019-03-30Make --help return 0 after printing the help messageAndrew Waterman1-4/+11
2019-03-27Respect interrupt priorities even when not delegatedAndrew Waterman1-9/+13
The spec says that e.g. MEI takes priority over SEI. We got this right in the common case that SEI is delegated to S-mode, but we reversed it in the undelegated case. The destination privilege was correct, so this wasn't much of a problem, but it is technically noncompliant. Resolves #288
2019-03-12include sys/types.h for suseconds_t (#285)nmeum1-0/+1
This fixes the build on Alpine Linux (which uses musl libc).
2019-03-04Implement halt groups (#280)Tim Newsome3-176/+649
* Update debug_defines from latest spec. * Implement halt groups. This lets the debugger halt multiple harts near simultaneously. * Revert encoding, which I updated accidentally.
2019-02-28Further fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-3/+4
ee6fe6501a21ea8d167b6a5048527ba9eb924878 didn't get this right, as it failed to add the offset to the address when checking each 4-byte sector of the access against hte PMPs.
2019-02-19Fix small bug in debug example. (#277)Tim Newsome1-7/+9
23 is the wrong line number. Avoid future problems by using a label.
2019-02-04Fix use of old name `riscv-isa-run` (#269)Luís Marques1-1/+1
2019-02-04Merge pull request #274 from hakrdinesh/masterAndrew Waterman3-1/+22
openbsd port of spike and its build documentation
2019-02-04need to install dtc pkg on openbsdDinesh Thirumurthy1-2/+2
2019-02-04doc typo fix on README.md, sorry.Dinesh Thirumurthy1-1/+1
2019-02-04build instructions for openbsdDinesh Thirumurthy1-0/+14
2019-02-04fixing compilation errors on openbsdDinesh Thirumurthy1-0/+7
2019-02-04bash can be at /usr/local/bin, on openbsdDinesh Thirumurthy1-1/+1
2019-01-28Fix PMP checks for partially-matching accesses (#270)Andrew Waterman2-8/+21
PMP checks should unconditionally fail if the PMP matches part of, but not all of, an access. We got this right, but went too far: we checked whether _any_ PMP matches in this manner. In fact, only the first PMP that maches any of the bytes should be checked in this manner.
2019-01-09Merge pull request #265 from riscv/debug_testTim Newsome7-38/+98
Add --dmi-rti and --abstract-rti to test OpenOCD.
2018-12-21Reserve the PMP R=0 W=1 combinationAndrew Waterman1-2/+5
This was a post-v1.10 amendment to the privileged spec. https://github.com/riscv/riscv-isa-manual/commit/059f64c941856f249d8a0647e23e150dbdb1f62c
2018-12-19Flush I/O buffers before forkingAndrew Waterman1-0/+1
This prevents duplicate I/Os to buffered streams early in the program.
2018-12-13Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome7-38/+98
Optionally make spike behave more like real hardware, to automatically test OpenOCD's handling of such hardware.
2018-12-03Correct address autoincrement calls. (#263)Tim Newsome1-2/+5
Now we do what the spec says we should do. This ended up not having any effect on the current way OpenOCD performs system bus accesses.
2018-11-09commands render correctly in README.md now, included in code blocknaufal1-1/+2
2018-11-06Report misaligned-address exception on failed store-conditionalsAndrew Waterman2-14/+8
Previously, the exception would only be raised if the store-conditional would have succeeded.
2018-10-19Merge pull request #247 from heshamelmatary/noisy_untilPalmer Dabbelt2-6/+20
Provide a noisy until interactive command
2018-10-18Provide a noisy until interactive commandHesham Almatary2-6/+20
This is useful for example when the trace until a PC value needs to be extracted (#246)
2018-10-04Set marchid to assigned value 5Andrew Waterman1-1/+1
https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md TODO: allow Spike users to override marchid/mvendorid/mimpid to mimic their hardware implementations more closely.
2018-10-03fix disassembly of c.addi4spnAndrew Waterman1-1/+1
Resolves #243
2018-09-27Add comment about CSR read side effectsAndrew Waterman1-0/+3
2018-09-25For backwards compatibility, reset PMP to permit all accessesAndrew Waterman1-0/+3
2018-09-25Add PMP supportAndrew Waterman4-24/+147
2018-09-24Add "--log-cache-miss" option to generate a log of cache miss. (#241)takeoverjp3-2/+19
* Add "--log-cache-miss" option to generate a log of cache miss. - This option must be used with "--ic" and/or "--dc" options to enable cache simulation. - This option is useful with "-l" option to understand which instruction has caused the cache miss. * Modify log format of cache miss to reduce log size.
2018-09-12Update READMEAndrew Waterman1-9/+6
2018-09-06Merge pull request #235 from riscv/sbaTim Newsome1-1/+1
Fix cut-and-paste bug in 64-bit SBA loads.
2018-09-05Fix cut-and-paste bug in 64-bit SBA loads.Tim Newsome1-1/+1
Fixes #234.
2018-08-24Handle spike-dasm inputs with leading 0x correctlyAndrew Waterman1-9/+17
2018-08-23Add dummy custom debug registers, to test OpenOCD. (#233)Tim Newsome2-0/+18
2018-08-23Fix several disassembler bugsAndrew Waterman2-57/+89
h/t Shane Lardinois
2018-08-23Add --disable-dtb option to suppress writing the DTB to memoryAndrew Waterman3-2/+11
2018-08-22Make IRQ_COP read-only/undelegable unless coprocessor is presentAndrew Waterman1-1/+2
2018-08-21Instantiate disassembler after max_xlen is knownAndrew Waterman1-1/+5
This fixes RVC disassembly. It's done in a way that doesn't break 2cd60b277e909a5599ca48e4561cbfbc61460186
2018-08-17Don't increment instret immediately after it is written (#231)Andrew Waterman1-0/+6
This brings Spike into compliance with this clause in the spec: https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96
2018-08-10Fix 2 trigger corner cases. (#229)Tim Newsome2-6/+14
1. When hitting a trigger during a single step, dcsr.cause must reflect the trigger not the step. 2. Also check for triggers on accesses that require a slow path fetch.
2018-07-31Make sstatus.MXR readableAndrew Waterman1-1/+1
h/t @taoliug
2018-07-23Fix using the uninitialized disassemble object. (#220)SeungRyeol Lee1-1/+1
This fixes runtime crash when custom extension registers its disassembly.
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman9-11/+34
- Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612) - Don't yield reservation on exceptions (it's no longer required).
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