Age | Commit message (Collapse) | Author | Files | Lines | |
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2022-06-03 | Simplify misaligned_load()trigger_priority | Tim Newsome | 2 | -15/+4 | |
Give it the same interface as load_slow_path(), so there's no need to worry about endianness in either of those two functions. | |||||
2022-06-03 | Simplify handling of misaligned loads/stores | Andrew Waterman | 1 | -48/+34 | |
Move all misaligned handling into the slow path. This is justifiable on the basis that, on average, they account for a significant minority of accesses even on systems that support them with reasonable performance. | |||||
2022-06-03 | Make check_trigger_address_before() return void. | Tim Newsome | 2 | -18/+12 | |
It already throws the exception when it needs to. | |||||
2022-06-03 | Fix trigger store priority. | Tim Newsome | 2 | -16/+39 | |
Fixes the other half of #971. Compared the start of this set of changes, it now takes 11% longer to run the towers benchmark (with 22 discs). | |||||
2022-06-03 | Make templated store_fast() for use with store_func() | Tim Newsome | 1 | -29/+39 | |
Easier to read, maintaing, compiler errors, etc. | |||||
2022-06-03 | Check for alignment in load_slow_path(). | Tim Newsome | 2 | -8/+29 | |
When the slow path occurs, don't check for alignment in load_fast(). I haven't tested different endianness. With this change, #971 is resolved for loads. | |||||
2022-05-26 | Turn load_fast() from macro into template | Tim Newsome | 1 | -31/+36 | |
Easier to edit, better error messages from compiler, etc. | |||||
2022-05-26 | Check early for trigger address in fast load_func() | Tim Newsome | 1 | -1/+8 | |
2022-05-26 | Use `size` variable consistently. | Tim Newsome | 1 | -8/+8 | |
Slightly more readable than sizeof(type##_t) everywhere. | |||||
2022-05-26 | Check address for triggers before the access happens. | Tim Newsome | 2 | -0/+22 | |
Only in slow path right now. | |||||
2022-05-26 | Add address_match() to triggers. | Tim Newsome | 2 | -0/+44 | |
In preparation for checking accesses before they happen, when we only know the address and not the data. | |||||
2022-05-26 | Use idiomatic iteration. | Tim Newsome | 1 | -5/+5 | |
2022-05-16 | Merge pull request #1003 from vogelpi/include-headers | Andrew Waterman | 1 | -0/+3 | |
Include recently added headers in riscv/riscv.mk.in | |||||
2022-05-16 | Include recently added headers in riscv/riscv.mk.in | Pirmin Vogel | 1 | -0/+3 | |
2022-05-13 | Merge pull request #997 from riscv-software-src/simplify-decode_insn | Andrew Waterman | 4 | -22/+21 | |
Simplify decode_insn and insn_desc_t | |||||
2022-05-13 | Fix disassembly of custom instructions that overlap standard ones (#999) | Andrew Waterman | 1 | -3/+10 | |
Iterate over the instruction chains in reverse order, prioritizing the last call to `disassembler_t::add_insn`. To preserve behavior for the standard instructions, reverse the order in which we add instructions in the `disassembler_t` constructor. Supersedes #995. | |||||
2022-05-13 | Disassemble Zicbop/Zihintpause HINT instructions (#1000) | Andrew Waterman | 1 | -0/+9 | |
We do not condition them on Zicbop/Zihintpause because, definitionally, all implementations provide them. | |||||
2022-05-12 | Update README to reflect recently added extensions | Andrew Waterman | 1 | -0/+3 | |
2022-05-12 | Add missing Zicbom and Zicbop extensions to disassembler fallback | Andrew Waterman | 1 | -1/+1 | |
2022-05-12 | Add missing Q, H, and Svinval extensions to disassembler fallback | Andrew Waterman | 1 | -1/+1 | |
2022-05-12 | Remove now-unnecessary null check from decode_insn | Andrew Waterman | 1 | -2/+2 | |
Fixes bug introduced in 5b7cdbe1cf75112bd2a472b7490b15fa7078d798 | |||||
2022-05-12 | Assert that nullptrs can't make their way into the instructions list | Andrew Waterman | 1 | -0/+2 | |
2022-05-12 | Remove insn_func_t::supported field | Andrew Waterman | 4 | -13/+8 | |
The field is rendered unnecessary by 11f5942b7d8211e61b5ad9259d118033692c0759. Undoes some changes from 750f008e723bb3b20cec41a47ed5cec549447665. | |||||
2022-05-12 | Don't register instructions that aren't supported | Andrew Waterman | 1 | -8/+10 | |
These add to the length of the instruction list without providing an apparent benefit. | |||||
2022-05-11 | Merge pull request #992 from rbuchner-aril/rb-pbmte | Andrew Waterman | 4 | -6/+37 | |
Fix for issue #990, implements the PBMTE bit in the henvcfg /menvcfg reisters | |||||
2022-05-11 | Check for reserved PBMT values during tablewalks and fault if found | Ryan Buchner | 1 | -0/+4 | |
See #990. | |||||
2022-05-11 | Switch from checking for SVPBMT extension to checking *ENVCFG values during ↵ | Ryan Buchner | 1 | -2/+4 | |
tablewalks Fix issue #990. | |||||
2022-05-11 | Add PBMTE bit to menvcfg and henvcfg mask values | Ryan Buchner | 1 | -4/+8 | |
Also make PBMTE set on reset for backward compatibility. Since before Spike proceeded as if these bits were set if the extension was enabled. | |||||
2022-05-11 | Change henvcfg csr to a henvcfg_csr_t | Ryan Buchner | 3 | -1/+22 | |
To do so implemented henvcfg_csr_t. henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0. | |||||
2022-05-11 | Merge pull request #994 from chihminchao/rvv-misc-2022-05-11 | Andrew Waterman | 1 | -0/+1 | |
rvv: fix the checking eew and elen for index load | |||||
2022-05-11 | rvv: fix the checking eew and elen for index load | Chih-Min Chao | 1 | -0/+1 | |
eew of index register can't be larger than elen ex: elen = 32, vloxei64.v is illegal Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2022-05-09 | Merge pull request #988 from riscv-software-src/factor-out-macros | Andrew Waterman | 3 | -2569/+2583 | |
Factor out P and V extension macros into their own headers | |||||
2022-05-05 | Factor out P extension macros into their own headerfactor-out-macros | Andrew Waterman | 2 | -500/+507 | |
No functional change. | |||||
2022-05-05 | Factor out V extension macros into their own header | Andrew Waterman | 2 | -2069/+2076 | |
No functional change. | |||||
2022-05-05 | Merge pull request #983 from soberl/epmp_updates_2 | Scott Johnson | 6 | -13/+131 | |
Implement Smepmp extension | |||||
2022-05-05 | Append smepmp extension 1.0 to the feature list | soberl | 1 | -0/+1 | |
2022-05-04 | Update pmpaddr_csr_t::access_ok() for ePMP on matching regions | soberl@nvidia.com | 1 | -5/+31 | |
2022-05-04 | Update mmu_t::pmp_ok() for ePMP in case matching region is not found | soberl@nvidia.com | 1 | -1/+5 | |
2022-05-04 | Update csr access rules for ePMP on pmpaddr and pmpcfg | soberl@nvidia.com | 1 | -7/+31 | |
2022-05-04 | Implement the new csr mseccfg for ePMP as dummy | soberl@nvidia.com | 4 | -0/+63 | |
2022-05-04 | Merge pull request #985 from riscv-software-src/trigger_hit | Andrew Waterman | 2 | -11/+18 | |
Implement mcontrol.hit bit | |||||
2022-05-04 | Fix the padding of register names in the log (#987) | Shaked Flur | 1 | -1/+1 | |
This fix print x5 as "x5 ", instead of "x 5". | |||||
2022-05-04 | Linking spike_dasm misses libriscv.a dependance (#986) | jmonesti | 1 | -1/+1 | |
Whereas spike-dasm.cc now instanciates an isa_parser_t, the dependance on libriscv.a has become unconditional. | |||||
2022-05-02 | Use MCONTROL_TYPE_MATCH macro instead of 2 | Tim Newsome | 1 | -1/+1 | |
2022-05-02 | Implement mcontrol trigger hit bit. | Tim Newsome | 2 | -1/+14 | |
2022-04-30 | Add missing description of --dtb in --help message | Andrew Waterman | 1 | -0/+1 | |
2022-04-22 | Add zknd zkne zknh zksed zksh disassembly support (#979) | Yan | 1 | -0/+70 | |
2022-04-22 | Remove mcontrol_t.h | Tim Newsome | 2 | -4/+1 | |
It was removed from the spec a long time ago. | |||||
2022-04-22 | Merge pull request #978 from rbuchner-aril/amo-order-change-patch | Scott Johnson | 1 | -6/+8 | |
Bug Fix for bug introduced in PR #976 | |||||
2022-04-22 | Remove maskmax as a variable. | Tim Newsome | 2 | -3/+2 | |