Age | Commit message (Collapse) | Author | Files | Lines |
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Several people have raised the concern that dynamically linking the
built-in components of Spike causes more headaches than it's worth.
IIRC, the only reason we did this is to better support the
`--extension=libfoo.so` feature.
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https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f#diff-2a8fece1cbcdf623cafbce866ea7d4d0R7
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The spec says that e.g. MEI takes priority over SEI. We got this right in
the common case that SEI is delegated to S-mode, but we reversed it in the
undelegated case.
The destination privilege was correct, so this wasn't much of a problem,
but it is technically noncompliant.
Resolves #288
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This fixes the build on Alpine Linux (which uses musl libc).
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* Update debug_defines from latest spec.
* Implement halt groups.
This lets the debugger halt multiple harts near simultaneously.
* Revert encoding, which I updated accidentally.
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ee6fe6501a21ea8d167b6a5048527ba9eb924878 didn't get this right,
as it failed to add the offset to the address when checking each
4-byte sector of the access against hte PMPs.
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23 is the wrong line number. Avoid future problems by using a label.
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openbsd port of spike and its build documentation
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PMP checks should unconditionally fail if the PMP matches part of, but
not all of, an access. We got this right, but went too far: we checked
whether _any_ PMP matches in this manner. In fact, only the first PMP
that maches any of the bytes should be checked in this manner.
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Add --dmi-rti and --abstract-rti to test OpenOCD.
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This was a post-v1.10 amendment to the privileged spec.
https://github.com/riscv/riscv-isa-manual/commit/059f64c941856f249d8a0647e23e150dbdb1f62c
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This prevents duplicate I/Os to buffered streams early in the program.
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Optionally make spike behave more like real hardware, to automatically
test OpenOCD's handling of such hardware.
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Now we do what the spec says we should do. This ended up not having any
effect on the current way OpenOCD performs system bus accesses.
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Previously, the exception would only be raised if the store-conditional
would have succeeded.
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Provide a noisy until interactive command
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This is useful for example when the trace until a PC value needs
to be extracted (#246)
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https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
TODO: allow Spike users to override marchid/mvendorid/mimpid to
mimic their hardware implementations more closely.
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Resolves #243
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* Add "--log-cache-miss" option to generate a log of cache miss.
- This option must be used with "--ic" and/or "--dc" options
to enable cache simulation.
- This option is useful with "-l" option to understand
which instruction has caused the cache miss.
* Modify log format of cache miss to reduce log size.
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Fix cut-and-paste bug in 64-bit SBA loads.
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Fixes #234.
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h/t Shane Lardinois
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This fixes RVC disassembly.
It's done in a way that doesn't break 2cd60b277e909a5599ca48e4561cbfbc61460186
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This brings Spike into compliance with this clause in the spec:
https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96
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1. When hitting a trigger during a single step, dcsr.cause must reflect
the trigger not the step.
2. Also check for triggers on accesses that require a slow path fetch.
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h/t @taoliug
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This fixes runtime crash when custom extension registers its
disassembly.
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- Use physical addresses to avoid homonym ambiguity (closes #215)
- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)
- Don't yield reservation on exceptions (it's no longer required).
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Update debug_defines.h
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Add support for hartselhi parsing, but other parts of the debug code
still don't support more than 1024 harts.
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By separating the simif_t declaration from the sim_t declaration, the
simif_t declaration no longer depends on fesvr header files. This
simplifies compilation of custom sim class implementations that don't
depend on fesvr.
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