aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-01-04triggers: refactor: add bool itrigger_t::simple_match()YenHaoChen2-1/+7
2023-01-03Make misa.C read-onlyAndrew Waterman1-6/+1
This resolves the issue discussed in #1201. Prior to 0adf9307, clearing misa.C would disable compressed instructions and increase IALIGN to 32. Afterwards, clearing misa.C had essentially no effect because Zca and friends would stay enabled. While AFAICS this isn't technically incorrect, it certainly doesn't follow the principle of least surprise. Instead, remove the feature to toggle misa.C. The effect is that misa.C is 1 iff C is included in the ISA string, and IALIGN is independent of misa.C: specifically, IALIGN is 16 iff Zca is present. (And of course C implies Zca.) Removing the alignment check on misa writes is not a separate commit because these two changes should be made atomically. Not checking the alignment on misa writes goes hand-in-hand with misa.C being read-only.
2023-01-03Merge pull request #1205 from riscv-software-src/reservableAndrew Waterman5-44/+50
Add method to probe which memory regions are reservable
2023-01-03Support pte load/store from mmio regionsJerry Zhao1-2/+2
2023-01-03Pull pte load/store into methods of mmu_tJerry Zhao2-18/+54
2023-01-03Add method to probe which memory regions are reservableJerry Zhao3-7/+13
Default reservable regions is the same as before
2023-01-03Remove extraneous semicolon from simif.hJerry Zhao1-1/+1
2023-01-03Specify addresses are physical for simif_t member functionsJerry Zhao5-37/+37
2023-01-02Merge pull request #1177 from YenHaoChen/pr-mcontrol6Scott Johnson3-59/+106
Support mcontrol6 trigger
2022-12-29Make obvious that PC alignment mask is a function of IALIGNAndrew Waterman1-1/+2
No functional change.
2022-12-29Merge pull request #1197 from riscv-software-src/wfiAndrew Waterman3-0/+10
Prevent processor_t from retiring instructions after a WFI
2022-12-27Prevent processor_t from retiring instructions after a WFIJerry Zhao3-0/+10
2022-12-27Merge pull request #1196 from riscv-software-src/readme_addressAndrew Waterman1-3/+3
Change address used in gdb debug example.
2022-12-27Change address used in gdb debug example.Tim Newsome1-3/+3
PR #889 put a UART at 0x10000000, which conflicts with the old address. Fixes #1179.
2022-12-24Merge pull request #1195 from riscv-software-src/mmio_typeAndrew Waterman3-1/+11
Expose access type in simif_t mmio_load interface
2022-12-23Merge pull request #1194 from riscv-software-src/clean-up-makefilesAndrew Waterman6-57/+1
Remove dead code in Makefiles
2022-12-23Add mmio_fetch to simif_t to distinguish between fetch/load for mmio accessesJerry Zhao3-1/+11
2022-12-22Remove dead code in Makefile.inAndrew Waterman1-3/+0
2022-12-22Remove non-installed header lists from Makefile fragmentsAndrew Waterman6-54/+1
It's just dead code. (Dependences on headers are auto-generated as `.d` files.)
2022-12-21Merge pull request #1192 from riscv-software-src/improve-histogramAndrew Waterman2-3/+7
Slightly improve histogram feature
2022-12-21Merge pull request #1191 from riscv-software-src/always_histogramAndrew Waterman5-37/+7
Support histogram feature without configure option
2022-12-21Merge pull request #1147 from riscv-software-src/extension-namespaceAndrew Waterman1-1/+1
Support more than 65 Z* extensions
2022-12-21Merge pull request #1193 from riscv-software-src/fix-build-nondeterminismAndrew Waterman1-0/+1
Fix build nondeterminism by deleting archives before recreating
2022-12-21Fix build nondeterminism by deleting archives before recreatingAndrew Waterman1-0/+1
Otherwise, `ar rcs` will add to the previous archive, creating the possibility of multiple functions with the same name in the archive. The linker might not choose the most recent version, resulting in undefined behavior.
2022-12-21Speed up histogramming by changing data structureAndrew Waterman1-1/+1
Since we no longer rely on the map's order, use unordered_map.
2022-12-21Sort histogram printout count, rather than addressAndrew Waterman1-2/+6
2022-12-21Remove --enable-histogram optionAndrew Waterman4-29/+0
It's now redundant.
2022-12-21Only clear logging structures if logging is enabledAndrew Waterman1-2/+5
This speeds up histogramming when logging is disabled, with almost no slowdown for the logging case.
2022-12-21Always use slow path for histogrammingAndrew Waterman1-2/+2
Speeds up fast path after unconditionally enabling histogram.
2022-12-21Support histogram regardless of configure flagAndrew Waterman2-4/+0
2022-12-20Merge pull request #1190 from riscv-software-src/reduce-compile-timeAndrew Waterman6-44/+72
Reduce compile time increase introduced by #1189
2022-12-20Reduce compile time increase introduced by #1189Andrew Waterman6-44/+72
Generate one object file per instruction rather than two, which reduces the overhead of invoking the compiler so many times. This also reduces the size of the (unstripped) binary substantially.
2022-12-21triggers: add mcontrol6 triggerYenHaoChen3-1/+53
2022-12-21triggers: refactor: add mcontrol_common_t::legalize_match() functionYenHaoChen2-14/+17
2022-12-21triggers: refactor: remove redundant namespace qualifiersYenHaoChen1-7/+7
2022-12-21triggers: refactor: extract mcontrol_common_t from mcontrol_tYenHaoChen2-6/+10
2022-12-21triggers: refactor: update trigger_t::mode_match()YenHaoChen1-5/+5
2022-12-21triggers: refactor: add trigger_t::mode_match() functionYenHaoChen2-14/+14
2022-12-20Support more than 65 Z* extensionsAndrew Waterman1-1/+1
The isa_extension_t enum already has 44 extensions. In not too long, the enum will grow in size to 65, when it will collide with the 'A' extension. Fix that preemptively by starting after 'Z'. This approach will run out of steam at 165 extensions because we are using `unsigned char` to represent extensions, but opefully we will have retired by that point. In seriousness, we will probably need to refactor the extension_enabled logic at some point in the future (e.g. when the configuration structure is finally added) and at that point we should lift the `char` limit.
2022-12-21triggers: refactor: move m/s/u/vs/vu to trigger_tYenHaoChen1-15/+6
2022-12-21triggers: refactor: add mcontrol.vs and mcontrol.vuYenHaoChen2-3/+4
2022-12-21triggers: refactor: cleaner vs and vu checkingYenHaoChen1-8/+4
2022-12-20Merge pull request #1189 from riscv-software-src/always_commitlogAndrew Waterman17-129/+112
Always support commit-logging without performance penalty
2022-12-20Always build with commit logging supportJerry Zhao6-37/+3
2022-12-20Add logged instruction variants to insn_desc_tJerry Zhao4-20/+49
2022-12-20Add logged variants of insn templatesJerry Zhao6-18/+36
2022-12-20Replace compile-time commitlog check with runtime check for vector writesJerry Zhao1-3/+1
2022-12-20Replace compile-time conditional with run-time conditional for load/store ↵Jerry Zhao1-19/+4
logging
2022-12-20Split execute_insn into fast and logged variantsJerry Zhao1-14/+9
Fast variant should only be used when logging is disabled
2022-12-20Force slow-path when commit-logging is enabledJerry Zhao1-1/+1