aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2022-04-22Remove mcontrol_t.type.Tim Newsome2-3/+2
2022-04-22Whitespace fix.Tim Newsome1-1/+0
2022-04-21Pass acutally_store from store_func to misaligned_storeRyan Buchner1-1/+1
2022-04-21Add actually_store tag to misaligned_store functionRyan Buchner1-2/+2
2022-04-21Modify store_func to throw fault if misaligned and require_alignment=trueRyan Buchner1-2/+4
2022-04-21Set require alignment to true on the 'fake' store in amo_func.Ryan Buchner1-1/+1
2022-04-21Add require_alignment tag to store_funcRyan Buchner1-1/+1
2022-04-14Merge pull request #975 from plctlab/plct-code-styleAndrew Waterman6-302/+324
2022-04-14add support for overlap instructionsWeiwei Li5-9/+28
2022-04-14fix style problems in decode.h and processor.ccWeiwei Li2-293/+296
2022-04-13Merge pull request #954 from rswarbrick/more-cfgAndrew Waterman4-54/+80
2022-04-13Merge pull request #976 from rbuchner-aril/amo-attr-fixAndrew Waterman2-21/+28
2022-04-13Adjust indentation in store_slow_path and store_funcRyan Buchner2-18/+18
2022-04-13Skip storing in store_func if actually_store is false, add a fake store at st...Ryan Buchner2-1/+8
2022-04-12Add actually_store tag to store_func and store_slow_pathRyan Buchner2-4/+4
2022-04-12Move real_time_clint into cfg_tRupert Swarbrick4-9/+12
2022-04-12Move varch into cfg_tRupert Swarbrick4-6/+9
2022-04-12Remove nprocs from cfg_tRupert Swarbrick3-12/+11
2022-04-12Move hartids into cfg_tRupert Swarbrick4-18/+28
2022-04-12Move the "default hartids" logic from sim.cc into spike.ccRupert Swarbrick2-10/+19
2022-04-12Slightly refactor --hartids parsing in spike.ccRupert Swarbrick1-13/+16
2022-04-12Move start_pc into cfg_tRupert Swarbrick4-8/+7
2022-04-12Fix debug messages about invalid pmpregions/mmu-typesRupert Swarbrick1-2/+2
2022-04-11Change processor_t to hold a pointer to an isa_parser_t (#973)Rupert Swarbrick4-18/+18
2022-04-11Split mem layout computation in spike.cc (#957)Rupert Swarbrick2-27/+65
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson10-229/+389
2022-04-11Merge pull request #972 from scottj97/fix-hgatpScott Johnson1-1/+1
2022-04-11Fix hgatp CSR writeAnup Patel1-1/+1
2022-04-11Merge pull request #968 from 4vtomat/masterAndrew Waterman1-84/+20
2022-04-10Adjust the access index of vs2 to zero in vmv_x_s.h (#969)Brandon Wu1-21/+17
2022-04-09Replaced vector loop compare body with newly defined macro4vtomat1-90/+11
2022-04-09Adding new macro to replace repetitive code4vtomat1-0/+15
2022-04-07Merge pull request #966 from riscv-software-src/fix-riscv-buildAndrew Waterman10-12/+11
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman9-11/+11
2022-04-07Fix build of dtm.cc on RISC-V targetsAndrew Waterman1-1/+0
2022-04-07Pass ref instead of pointer to trigger_updated()Tim Newsome3-5/+5
2022-04-07Add const to pointers where possible.Tim Newsome2-27/+27
2022-04-07Add module_t::~module_t()Tim Newsome2-0/+9
2022-04-06mmu: support asid/vmid (#928)Chih-Min Chao3-3/+13
2022-04-06Tick devices even when tohost != 0Andrew Waterman1-9/+10
2022-04-05Merge pull request #960 from marcfedorow/upstreamAndrew Waterman3-6/+15
2022-04-05Make triggers a vector of trigger_t.Tim Newsome3-3/+3
2022-04-05Abstract away access to load/store/execute bits.Tim Newsome3-18/+24
2022-04-05Make trigger_t::tdata{1,2}_{read,write} virtualsTim Newsome1-4/+9
2022-04-05Make chain into chain() for all triggers.Tim Newsome2-6/+10
2022-04-05Make triggers::module_t::triggers private.Tim Newsome4-6/+10
2022-04-05Move num_triggers knowledge into triggers.hTim Newsome4-10/+8
2022-04-05Don't access triggers vector directly from csrs.cc.Tim Newsome3-4/+29
2022-04-05Move trigger match logic into triggers.ccTim Newsome4-49/+71
2022-04-05module_t::trigger_match -> memory_access_matchTim Newsome3-4/+4
generated by cgit v1.1 at 2024-09-10 05:20:35 +0000