Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2020-05-27 | rvv: index register doesn't care about NFsifive/rvv0.9-phase2 | Chih-Min Chao | 1 | -3/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-27 | rvv: fix ext alignment checking for src and dst | Chih-Min Chao | 1 | -0/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-27 | rvv: v[z|s]ext: remove redundant requires | Dave.Wen | 1 | -2/+0 | |
2020-05-25 | sf: fix f16_to_ui8 | Chih-Min Chao | 1 | -1/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-25 | rvv: add e8 type for scale | Chih-Min Chao | 2 | -3/+18 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-25 | softfloat: FIXME quick work around to pass the compilation. Not guarantee ↵ | Dave.Wen | 1 | -1/+1 | |
the functional correctness. | |||||
2020-05-25 | softfloat: add f16_to_[u]i8 into targets | Dave.Wen | 1 | -0/+2 | |
2020-05-25 | rvv: fix wrong vill checking | Chih-Min Chao | 7 | -6/+9 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-24 | rvv: support [u]i8 type | Chih-Min Chao | 16 | -3/+59 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-24 | sf: add f16_to_[u]i8 interface | Chih-Min Chao | 4 | -0/+116 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-24 | rvv: add missing lmul/vsew/elen checking | Chih-Min Chao | 1 | -1/+6 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-22 | rvv: disasm: fix vsetvli | Chih-Min Chao | 1 | -1/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-22 | rvv: totally remove vlmul field | Chih-Min Chao | 2 | -26/+6 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-22 | rvv: remove remove vlmul | Chih-Min Chao | 10 | -31/+29 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: dont't handle slen != vlen | Chih-Min Chao | 1 | -8/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: remove duplicated CI_BI macro | Chih-Min Chao | 1 | -10/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: refine comparision checking | Chih-Min Chao | 1 | -8/+6 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: remove vmlen | Chih-Min Chao | 18 | -49/+40 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: refine vl length and elemnet size checking | Chih-Min Chao | 5 | -9/+8 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: update the exception rules for v[m]adc/v[m]sbc | Dave.Wen | 1 | -4/+12 | |
2020-05-21 | rvv: fix index load/store emul/nf checking | Chih-Min Chao | 1 | -0/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: fix vms[bio]f.m checking rule | Chih-Min Chao | 3 | -9/+12 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: src can't overlap dst for ext | Chih-Min Chao | 1 | -0/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: fix index checking | Chih-Min Chao | 1 | -1/+5 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: v[z|s]ext | Dave.Wen | 1 | -40/+6 | |
2020-05-21 | rvv: index should align vemul | Chih-Min Chao | 1 | -1/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-21 | rvv: fix atomic | Chih-Min Chao | 1 | -3/+9 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-20 | wip: v[z|s]ext | Dave.Wen | 1 | -6/+47 | |
2020-05-20 | rvv: fix index load/store | Chih-Min Chao | 1 | -26/+24 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-20 | rvv: refine st_index | Chih-Min Chao | 9 | -192/+18 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-20 | rvv: refine ld_index | Chih-Min Chao | 5 | -98/+14 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-20 | add configurable LR/SC reservation set | Dave.Wen | 7 | -11/+96 | |
2020-05-20 | rvv: make overlap handling zero size | Chih-Min Chao | 1 | -4/+5 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-20 | rvv: remove debug | Chih-Min Chao | 1 | -1/+0 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-20 | rvv: fix out of range checking unit/strided | Chih-Min Chao | 1 | -3/+3 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-20 | rvv: wrap vm checking | Chih-Min Chao | 1 | -14/+8 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-20 | rvv: refine overlapd and align checking | Chih-Min Chao | 1 | -38/+43 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-19 | fix clang compile error wthin FDT parsing | Scott Beamer | 2 | -7/+7 | |
2020-05-19 | Hardwire mstatus.[sie,spie] to zero if 'S' mode absent | Udit Khanna | 1 | -3/+2 | |
2020-05-19 | Implement coarse-grain PMP matching logic | Andrew Waterman | 1 | -6/+6 | |
2020-05-19 | Implement CSR read/write behavior for coarse-grain PMP | Andrew Waterman | 2 | -2/+11 | |
2020-05-19 | Implement configurable PMP count | Andrew Waterman | 1 | -6/+16 | |
If no PMPs exist, simply deny access to the registers. If some but not all PMPs exist, the others are hardwired to 0. | |||||
2020-05-19 | Disable PMP checks when configuration includes zero PMP registers | Andrew Waterman | 1 | -1/+1 | |
2020-05-19 | Support consuming PMP number and granularity from DTB | Andrew Waterman | 3 | -0/+37 | |
The feature itself isn't implemented yet. | |||||
2020-05-19 | Rename n_pmp constant to max_pmp | Andrew Waterman | 3 | -12/+12 | |
2020-05-19 | fdt: add pmp granularity function | Chih-Min Chao | 2 | -3/+25 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-19 | fdt: add pmp parsing helper | Chih-Min Chao | 2 | -1/+17 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-19 | fdt: restructure dtb create and config flow | Chih-Min Chao | 3 | -20/+51 | |
1. pass dtb option from constructor 2. separate dtb generation from rom initialization 3. setup clint base from dtb Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-19 | fdt: option: add --dtb option to specify dtb binary file | Chih-Min Chao | 3 | -2/+25 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-19 | fdt: add clint base address parsing helper | Chih-Min Chao | 2 | -0/+65 | |
borrow from OpenSBI Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> |