rocket-tools/riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-05-19	fdt: import fdt library from OpenSBI	Chih-Min Chao	22	-3/+5588
2020-05-19	Add missing stdexcept imports	Schuyler Eldridge	2	-0/+2
2020-05-19	rvv: fix widen checking	Chih-Min Chao	2	-4/+11
2020-05-19	rvv: store eew and emul to P.VU for unit/stride load/store	Chih-Min Chao	2	-23/+22
2020-05-18	rvv: fix unit/stride emul calculation	Chih-Min Chao	1	-3/+3
2020-05-18	rvv: fix compiler warning	Chih-Min Chao	1	-1/+1
2020-05-18	rvv: fix unit/strided load/store checking rule	Chih-Min Chao	1	-29/+18
2020-05-18	rvv: disasm: add missing .wx format	Chih-Min Chao	1	-1/+3
2020-05-18	rvv: disasm: fix unorder index store	Chih-Min Chao	1	-1/+1
2020-05-18	rvv: vid's mlen overlap checking	Dave.Wen	1	-1/+1
2020-05-18	rvv: MLEN=1 overlapping	Dave.Wen	1	-4/+4
2020-05-17	rvv: mlen=1 WIP	Dave.Wen	2	-4/+5
2020-05-14	rvv: disasm: fix amo format	Chih-Min Chao	1	-1/+1
2020-05-14	rvv: amo: only allow 32/64 bit element	Chih-Min Chao	2	-16/+1
2020-05-14	rvv: add vzext/vsext	Chih-Min Chao	8	-0/+44
2020-05-14	rvv: op: reorder vext	Chih-Min Chao	1	-18/+18
2020-05-14	rvv: dont't explicit throw exception	Chih-Min Chao	1	-1/+1
2020-05-14	disasm: refine structure name	Chih-Min Chao	1	-3/+3
2020-05-14	rvv: add lmul=1 (m0) in disasm message	Dave.Wen	1	-19/+17
2020-05-14	rvv: fix the fractional lmul	Dave.Wen	3	-11/+22
2020-05-13	rvv: wrong operation to the fractional LMUL bit	Dave.Wen	1	-1/+1
2020-05-13	rvv: amo: fix wrong index eew	Chih-Min Chao	27	-27/+27
2020-05-13	rvv: change to 0.9amo	Chih-Min Chao	49	-102/+254
2020-05-13	rvv: amo pre-0.9	Chih-Min Chao	14	-0/+116
2020-05-13	rvv: fractional_lmul when lmul < 1	Dave.Wen	5	-12/+42
2020-05-13	vtype: fix the vta and vma functions and debugging display	Dave.Wen	4	-3/+9
2020-05-13	eew: add eew	Dave.Wen	1	-8/+17
2020-05-13	eew: fix the eew=0 case	Dave.Wen	2	-13/+18
2020-05-12	rvv: add ext opcode	Chih-Min Chao	2	-0/+26
2020-05-12	rvv: op: change vfunary0 and funary1 func6 field	Chih-Min Chao	2	-50/+56
2020-05-12	rvv: ldst: add missng check for VI_LD	Chih-Min Chao	1	-2/+1
2020-05-11	rvv: change to 0.9 ldst	Chih-Min Chao	79	-516/+696
2020-05-07	rvv: add eew and lmul for vle/vse/vleff	Dave.Wen	4	-7/+39
2020-05-06	fractional_lmul: update the vtype register and alos remove the useless reg_mask	Dave.Wen	1	-1/+3
2020-05-04	zfh: implementation all instructions	Chih-Min Chao	37	-0/+206
2020-05-04	zfh: add fp16 disasm	Chih-Min Chao	1	-0/+38
2020-05-04	zfh: op: add scalar opcode	Chih-Min Chao	1	-0/+108
2020-04-29	zfh: zfh require F extension support	Chih-Min Chao	1	-0/+3
2020-04-27	rvv: align VCSR with upstream	Chih-Min Chao	2	-15/+13
2020-04-27	parse: refine error format reporting	Chih-Min Chao	1	-10/+24
2020-04-27	rvv: commitlog: fix comparision dst information	Chih-Min Chao	3	-6/+9
2020-04-24	rvv: commitlog: fix missing informaiton for slide1	Chih-Min Chao	4	-12/+12
2020-04-24	rvv: commitlog: fix dst information for int comparison	Chih-Min Chao	1	-20/+40
2020-04-23	build: quota string with [] to avoid part of string missing	Chih-Min Chao	1	-1/+1
2020-04-23	rvv: fix vfncvt.xu.f.w for fp16	Chih-Min Chao	1	-1/+1
2020-04-23	rvv: aad fp16 support for vfwxxx.[wv]v	Chih-Min Chao	10	-8/+47
2020-04-22	rvv: simplify f16_to_[u]i16 implementation	Chih-Min Chao	4	-97/+2
2020-04-22	rvv: fix segment load/store nf checking	Chih-Min Chao	2	-9/+11
2020-04-21	rvv: fix vfmv for fp16	Chih-Min Chao	3	-13/+36
2020-04-21	rvv: fix vfmerge.vfm for fp16	Chih-Min Chao	1	-2/+15