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2023-12-11Remove in-tree libfdt, rely on system-installed libfdtnolibfdtJerry Zhao21-5574/+46
2023-12-11Merge pull request #1313 from endeneer/fdt-parse-clint-sifiveJerry Zhao1-1/+1
riscv: sim.cc: Parse for "sifive,clint0" if "riscv,clint0" is absent
2023-12-11Merge pull request #1314 from endeneer/fdt-parse-plic-sifiveJerry Zhao1-1/+2
riscv: sim.cc: Parse for other compatible strings if "riscv,plic0" is absent
2023-12-11Merge pull request #1448 from ved-rivos/adue_fixAndrew Waterman2-8/+19
A/D updates in G-stage PTE
2023-12-11riscv: sim.cc: Parse for "sifive,plic-1.0.0" if "riscv,plic0" is absentTan En De1-1/+2
"riscv,plic0" and "sifive,plic-1.0.0" in device tree's "compatible" string point to the same driver, as can be seen from drivers/irqchip/irq-sifive-plic.c in Linux kernel. https://github.com/torvalds/linux/commit/5873ba559101fa37ad9764e79856f71bf54021aa The other two "compatible" strings below isn't included, because of their different plic behavior (plic_edge_init instead of plic_init as explained in the Linux commit). - "andestech,nceplic100" - "thead,c900-plic" Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-11riscv: sim.cc: Parse for "sifive,clint0" if "riscv,clint0" is absentTan En De1-1/+1
"riscv,clint0" and "sifive,clint0" in device tree's "compatible" string point to the same driver, as can be seen from drivers/clocksource/timer-clint.c in Linux kernel. https://github.com/torvalds/linux/commit/2ac6795fcc085e8d03649f1bbd0d70aaff612cad Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-11Merge pull request #1506 from riscv-software-src/fix-1505Jerry Zhao1-2/+2
Don't enforce alignment constraints vwsll.v[xi] rs1 arg
2023-12-11Merge pull request #1526 from riscv-software-src/default_cfgJerry Zhao10-131/+68
Add default cfg_t and debug_module_config_t constructor to libriscv
2023-12-09Merge pull request #1532 from Madman-Hugo/fix-fmvh_x_dAndrew Waterman1-1/+1
fix fmvh_x_d.h rv32 sign-extended
2023-12-09fix fmvh_x_d.h rv32 sign-extendedMadman1-1/+1
Signed-off-by: Madman <1017747824@qq.com>
2023-12-08Rely on default initializer to provide debug_module_config_t defaultsJerry Zhao2-22/+2
2023-12-08Use brace initializers for debug_module_config_t defaultsJerry Zhao1-9/+9
2023-12-08Remove old explicit-fields cfg_t constructor, switch to default constructorJerry Zhao4-68/+3
2023-12-08Add cfg_t default constructor with default settingsJerry Zhao2-0/+22
2023-12-08Remove cfg_arg_t from cfg_tJerry Zhao7-31/+31
Argument parsing should be scoped to the code which constucts cfg_t
2023-12-08Merge pull request #1531 from riscv-software-src/zimop-v3Andrew Waterman7-10/+109
Add unratified Zimop extension
2023-12-08Add Zimop extensionAndrew Waterman6-1/+56
2023-12-08Fix formattingAndrew Waterman1-8/+8
2023-12-08Update encoding.hAndrew Waterman1-1/+45
2023-12-08Merge pull request #1530 from riscv-software-src/ci-commit-orderAndrew Waterman1-2/+2
Per-commit CI should start from oldest commit
2023-12-08Per-commit CI should start from oldest commitJerry Zhao1-2/+2
2023-12-08Merge pull request #1522 from ucb-bar/device-plugin-apiJerry Zhao8-11/+34
Fix Spike --device option to pass on args to downstream plugins
2023-12-08Fix Spike --device option to pass on args to downstream pluginsjoey03208-11/+34
2023-12-06Merge pull request #1523 from YenHaoChen/patch-1Andrew Waterman1-5/+5
miselect: support miselect when enabling smcsrind
2023-12-07refactor: single statement of declaration and initialization on miselect, ↵YenHaoChen1-6/+3
siselect, and vsiselect
2023-12-06miselect: support miselect when enabling smcsrindYenHaoChen1-0/+3
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
2023-12-01Merge pull request #1513 from riscv-software-src/sbbusyerrorAndrew Waterman3-32/+121
Add configurable system bus access delay
2023-12-01Test OpenOCD that can deal with sbbusyerror.Tim Newsome1-1/+1
2023-12-01Add SBA write delay.Tim Newsome2-8/+28
This is helpful to test OpenOCD behavior when sbbusyerror is set.
2023-12-01Add SBA read delay.Tim Newsome2-31/+100
This is helpful to test OpenOCD behavior when sbbusyerror is set.
2023-11-30Merge pull request #1517 from YenHaoChen/patch-1Andrew Waterman1-1/+1
typo: vwsll.vi: fix a typo on disassembling vwsll.vi
2023-12-01typo: vwsll.vi: fix a typo on disassembling vwsll.viYenHaoChen1-1/+1
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
2023-11-29Merge pull request #1516 from YenHaoChen/pr-dcsr-ebreakxAndrew Waterman1-4/+4
fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege modes
2023-11-29fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege ↵YenHaoChen1-4/+4
modes
2023-11-28Merge pull request #1514 from f0rget-the-sad/multi-rbAndrew Waterman2-1/+1
remote_bitbang: make send_buf class member
2023-11-28remote_bitbang: make send_buf class memberVolodymyr Fialko2-1/+1
Currently send buffer is static variable in function, which makes it's impossible to have multiple concurrent instances of remote bitbang class, since all of them would share this static buffer. Thus, make send_buf a class member. Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
2023-11-24Merge pull request #1511 from YenHaoChen/pr-stimecmpAndrew Waterman2-2/+7
stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in HS-mode
2023-11-24stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in ↵YenHaoChen2-2/+7
HS-mode The spec requires menvcfg.STCE=1 on accessing stimecmp or vstimecmp in a mode other than M-mode. The previous implementation does not check the permission on accessing vstimecmp in HS-mode. This commit fixes the issue by moveing the permission check from virtualized_stimecmp_csr_t to stimecmp_csr_t, which implements the vstimecmp.
2023-11-16Fix FMVP.D.X implementationAndrew Waterman1-1/+1
Resolves #1507
2023-11-15Don't enforce alignment constraints vwsll.v[xi] rs1 argAndrew Waterman1-2/+2
rs1 doesn't represent a vector arg in this case, so the instructions were broken for (rs1 % ceil(LMUL)) != 0. Resolves #1505
2023-11-10Merge pull request #1500 from riscv-software-src/debug_testsTim Newsome1-1/+1
Update debug smoketest action.
2023-11-10Update debug smoketest action.Tim Newsome1-1/+1
To get https://github.com/riscv-software-src/riscv-tests/pull/522, which fixes an intermittent failure.
2023-11-09Merge pull request #1498 from f0rget-the-sad/htif-stop-on-signalAndrew Waterman1-1/+1
fesvr/htif: allow exit on SIGINT.
2023-11-09fesvr/htif: allow exit on SIGINT.Volodymyr Fialko1-1/+1
Currently signal handler would call exit() only on second received signal, this prevent proper program cleanup. Instead use signal flag to exit loop. Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
2023-11-08Merge pull request #1490 from iamKarthikBK/masterAndrew Waterman8-4/+14
Add support for setting PMP Granularity over CLI
2023-11-04expose pmp granularity as a cli option.Karthik B K8-4/+14
PMP Granularity is made available as a command line option. The default value is 4 Bytes. The value can be changed by passing the option --pmp-granularity=<value> to spike. Signed-off-by: Karthik B K <karthik.bk@incoresemi.com>
2023-11-02Merge pull request #1491 from ved-rivos/zabhaAndrew Waterman25-1/+156
Add unratified Zabha extension
2023-11-02Add Zabha instructions to makeVed Shanbhogue1-0/+23
2023-11-02Add Zabha instructions to disasmVed Shanbhogue2-0/+29
2023-11-02Add enum for Zabha extensionVed Shanbhogue1-0/+1
generated by cgit v1.1 at 2024-06-29 08:12:26 +0000