index
:
rocket-tools/riscv-isa-sim.git
confprec
cs250
csr-init-fixes
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Expand
)
Author
Files
Lines
2014-02-07
Clear EVEC LSBs, which kindly prevents a segfault
Andrew Waterman
1
-2
/
+2
2014-02-06
Fix disassembly of JAL
Andrew Waterman
1
-1
/
+1
2014-02-06
commit missing definitions for uarch counters
Yunsup Lee
1
-0
/
+56
2014-02-03
Move half precision instructions, add vfmsv, vfmvv
Quan Nguyen
48
-137
/
+265
2014-01-31
Fix linking on Darwin
Andrew Waterman
3
-4
/
+3
2014-01-28
Disasm now translates xor x0,x0,x0 as a machine-generated bubble ("-").
Christopher Celio
1
-0
/
+1
2014-01-28
Force extension loaders to be linked in
Andrew Waterman
2
-6
/
+10
2014-01-26
Enable runtime loading of dynamic library with --extlib
Andrew Waterman
5
-158
/
+160
2014-01-26
Prefer libraries located in current directory
Andrew Waterman
1
-4
/
+4
2014-01-26
Eliminate hwacha <-> riscv circular dependence
Andrew Waterman
11
-110
/
+170
2014-01-26
Link subproject dynamic libraries correctly
Andrew Waterman
1
-7
/
+11
2014-01-25
Merge softfloat_riscv into softfloat
Andrew Waterman
18
-70
/
+13
2014-01-24
Require libdl for dynamic linking at runtime
Andrew Waterman
3
-15
/
+68
2014-01-24
Disassemble amoxor
Andrew Waterman
1
-0
/
+2
2014-01-24
Build and use shared libraries only
Andrew Waterman
3
-5
/
+6
2014-01-24
Build and use shared libraries
Andrew Waterman
3
-45
/
+45
2014-01-24
Handle CSR permissions correctly
Andrew Waterman
2
-6
/
+10
2014-01-21
Use auto-generated trap cause numbers
Andrew Waterman
2
-26
/
+52
2014-01-20
Merge branch 'confprec'
Quan Nguyen
78
-0
/
+353
2014-01-16
Initialize tohost and fromhost to zero
Andrew Waterman
1
-2
/
+5
2014-01-13
Improve performance for branchy code
Andrew Waterman
14
-85
/
+131
2013-12-17
Speed things up quite a bit
Andrew Waterman
7
-79
/
+118
2013-12-09
New RDCYCLE encoding
Andrew Waterman
9
-38
/
+39
2013-11-29
Remove debug printf in vsetprec
confprec
Quan Nguyen
1
-1
/
+0
2013-11-29
Add vsetprec instruction prototype
Quan Nguyen
5
-0
/
+17
2013-11-25
Update to new privileged ISA
Andrew Waterman
30
-402
/
+785
2013-11-24
Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEAD
Quan Nguyen
7
-4
/
+9
2013-11-21
fix slli/slliw encoding bug
Yunsup Lee
2
-4
/
+4
2013-11-05
add accelerator disabled cause
Yunsup Lee
1
-0
/
+1
2013-11-05
correctly trap when SR_EA is disabled
Yunsup Lee
4
-0
/
+4
2013-11-04
Fix declaration of half-precision instructions
Albert Ou
2
-0
/
+2
2013-11-04
Re-add Hwacha header file
Albert Ou
1
-0
/
+1
2013-11-04
Implement "half-baked" half-precision instruction subset for Hwacha
Albert Ou
39
-2
/
+336
2013-11-04
Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into confprec
Albert Ou
30
-180
/
+463
2013-10-28
include stdexcept
Yunsup Lee
1
-0
/
+1
2013-10-28
Pass target machine's return code back to OS
Andrew Waterman
3
-3
/
+4
2013-10-27
Add missing fcvt opcodes through riscv-opcodes
Quan Nguyen
1
-37
/
+4
2013-10-21
clarify vxcptsave/vxctkill semantics
Yunsup Lee
3
-3
/
+7
2013-10-18
implement vxcptsave/vxcptrestore
Yunsup Lee
4
-3
/
+82
2013-10-18
clean up SR_EA, the enable accelerator bit in status reg
Yunsup Lee
2
-5
/
+4
2013-10-18
more hwacha supervisor stuff
Yunsup Lee
6
-17
/
+21
2013-10-18
refactor disassembler, and add hwacha disassembler
Yunsup Lee
17
-144
/
+347
2013-10-18
can't execute frsr/fssr on ut
Yunsup Lee
3
-4
/
+0
2013-10-18
or into control thread's fp exceptions
Yunsup Lee
1
-4
/
+0
2013-10-17
Add empty opcode header files for half-precision
Quan Nguyen
34
-4
/
+37
2013-10-17
catch trap_illegal_instruction in hwacha
Yunsup Lee
1
-0
/
+4
2013-10-17
add hwacha exception support
Yunsup Lee
16
-38
/
+213
2013-10-17
fix custom-1 rocc encoding
Yunsup Lee
1
-1
/
+1
2013-10-16
fix maxvl calc logic
Yunsup Lee
1
-1
/
+5
2013-10-16
use reset virtual method
Yunsup Lee
3
-4
/
+5
[prev]
[next]