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AgeCommit message (Expand)AuthorFilesLines
2013-10-16use uint32_t for vlYunsup Lee1-1/+1
2013-10-16fix missing null check when there's no extensionYunsup Lee1-1/+2
2013-10-16revamp hwacha; now runs in physical modeYunsup Lee252-267/+718
2013-10-15Propogate the reset call to the extensions as well. Add reset function to ext...Stephen Twigg3-1/+8
2013-10-15Fix bug where xs2 was not being properly respected.Stephen Twigg1-1/+1
2013-10-10commit configure script; new configure option --enable-commitlogYunsup Lee2-0/+18
2013-09-27Added commit logging (--enable-commitlog). Also fixed disasm bug.Christopher Celio4-6/+54
2013-09-27Use WRITE_RD/WRITE_FRD macros to write registersAndrew Waterman141-185/+167
2013-09-26Bye, CBAndrew Waterman1-34/+0
2013-09-23fixes compile bug for not being able to find std::logic_errorScott Beamer1-0/+1
2013-09-23Fix Scott's deadlockAndrew Waterman3-7/+11
2013-09-22Adjust rocc_inst_t to properly extract fields due to the new ISA encoding.Stephen Twigg1-3/+3
2013-09-21Update ISA encoding and AUIPC semanticsAndrew Waterman3-168/+170
2013-09-15Add helper disassembly programAndrew Waterman2-0/+42
2013-09-15ISA changesAndrew Waterman1-2/+2
2013-09-11Add AMOXORAndrew Waterman3-16/+25
2013-09-11Implement zany immediatesAndrew Waterman39-459/+233
2013-09-10Don't tick HTIF as oftenAndrew Waterman1-4/+4
2013-09-10Add rd field to JAL; drop JAndrew Waterman6-42/+33
2013-08-18Renumber PCRsAndrew Waterman2-23/+20
2013-08-13Add test program for dummy roccAndrew Waterman1-0/+29
2013-08-13Implement RoCC and add a dummy RoCCAndrew Waterman11-40/+249
2013-08-11Instructions are no longer member functionsAndrew Waterman65-309/+337
2013-08-08Ignore JALR's effective address LSBAndrew Waterman1-1/+1
2013-08-08Disentangle some header filesAndrew Waterman2-1/+2
2013-08-08Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman4-5/+5
2013-08-08Swap J and JALR encodingAndrew Waterman1-2/+2
2013-07-31Fix eret (again)Quan Nguyen1-1/+1
2013-07-31Fix dumb ERET bugAndrew Waterman1-1/+1
2013-07-28Don't flush TLB on PTBR writes (only FATC)Andrew Waterman1-1/+1
2013-07-26New supervisor modeAndrew Waterman6-64/+81
2013-07-26Remove more vector stuffAndrew Waterman8-179/+54
2013-07-26Rename MFTX/MXTF to FMVAndrew Waterman6-8/+8
2013-07-26Rip out Hwacha for nowAndrew Waterman95-167/+74
2013-07-26Rip out RVC for nowAndrew Waterman41-118/+61
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman12-152/+134
2013-07-25Remove JALR static hintsAndrew Waterman5-22/+14
2013-07-22Kill spike when xspike is SIGINTedAndrew Waterman1-4/+10
2013-07-22Don't use stdout for debuggingAndrew Waterman1-4/+4
2013-07-22Add xspike programAndrew Waterman8-62/+219
2013-07-19Use calloc to allocate target memoryAndrew Waterman1-18/+7
2013-07-12Eliminate infinite loop in debug modeAndrew Waterman3-4/+12
2013-07-12Exit cleanly from debug consoleAndrew Waterman4-41/+24
2013-07-12Favor procs.size() over num_cores()Andrew Waterman1-3/+5
2013-07-12Fix SR_U64 bit being ignoredAndrew Waterman1-1/+1
2013-06-02make spike.o correctly depend on dispatch.hAndrew Waterman1-2/+2
2013-06-02use coreutils `seq' instead of hacky `range'Andrew Waterman2-11/+1
2013-05-15change riscv-isa-run to spike in documentationYunsup Lee2-3/+3
2013-05-15fix make issueYunsup Lee2-6/+6
2013-05-13change riscv-isa-run to spikeYunsup Lee4-4/+4
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