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2023-06-19Merge pull request #1364 from glg-rv/dev/glguida/amocasAndrew Waterman13-8/+263
Zacas extension
2023-06-19Merge pull request #1387 from ptomsich/ptomsich/add-zicond-to-disasmAndrew Waterman1-0/+5
Add Zicond to disassembler
2023-06-19Add Zicond to disassemblerPhilipp Tomsich1-0/+5
2023-06-19Merge pull request #1386 from ptomsich/ptomsich/fix-typo-in-checkPhilipp Tomsich1-1/+1
Makefile: fix type in check target
2023-06-19Implement Zacas extension.Gianluca Guida9-0/+108
2023-06-19regenerate enconding.hGianluca Guida1-1/+133
2023-06-19mmu: support load/store longer than 64-bits.Gianluca Guida1-2/+15
2023-06-19fesvr: support int128_t/uint128_tGianluca Guida2-5/+7
Also remove now duplicate definition for types.
2023-06-18Makefile: fix type in check targetPhilipp Tomsich1-1/+1
The check target processes the output using grep; however, one of the patterns misspelled 'Segmenetation'. Fixing the typo.
2023-06-18Merge pull request #1384 from riscv-software-src/remove-xbitmanipAndrew Waterman65-501/+18
Remove Xbitmanip instructions
2023-06-18Remove Xbitmanip from READMEAndrew Waterman1-14/+0
2023-06-18isa parser: reject Xbitmanip extensionsAndrew Waterman2-34/+1
2023-06-18Remove Xbitmanip from disassemblerAndrew Waterman1-33/+1
2023-06-18Remove Xbitmanip from instructions that belong to multiple extensionsAndrew Waterman14-30/+16
2023-06-18Remove instructions that belong only to XbitmanipAndrew Waterman47-390/+0
2023-06-18Add CMOV to overlap list, as it overlaps CZERO.EQZAndrew Waterman1-0/+1
2023-06-17Merge pull request #1385 from riscv-software-src/check-overlapAndrew Waterman8-164/+68
In CI, test that instruction opcodes don't overlap
2023-06-17Run 'make check' in CIAndrew Waterman1-0/+1
2023-06-17Add test that ensures opcodes don't overlap unless explicitly specifiedAndrew Waterman2-1/+59
2023-06-17Add C.EBREAK, C.JALR, and C.JR to overlap listAndrew Waterman1-0/+3
This isn't a functional change; we just failed to notate that C.EBREAK and C.JALR overlap C.ADD, and C.JR overlaps C.MV.
2023-06-17Restore MCPPBS unit-testing flowAndrew Waterman1-16/+5
2023-06-17Remove legacy debug testAndrew Waterman3-147/+0
These are now tested in CI using the riscv-tests repository.
2023-06-12Merge pull request #1377 from riscv-software-src/ci-thoroughJerry Zhao2-4/+20
Have CI run on each commit in a PR, instead of just the HEAD
2023-06-12ci: CI should check each commit in a PRJerry Zhao2-4/+20
test
2023-06-12Merge pull request #1376 from YenHaoChen/pr-cbo-regionAndrew Waterman1-1/+1
Fix: PMP checking region on CBO instructions
2023-06-12Fix PMP checking region of cache-block management instructionsYenHaoChen1-1/+1
The spec says "The PMP access control bits shall be the same for all physical addresses in the cache block [... else] the behavior of a CBO instruction is UNSPECIFIED." Thus, we only need to check the byte rs1 points to (instead of the entire cache block).
2023-06-07Merge pull request #1375 from demin-han/masterAndrew Waterman1-2/+2
Replace ternary operator with std:min
2023-06-08Replace ternary operator with std:mindemin.han1-2/+2
2023-06-06Merge pull request #1321 from plctlab/plct-bf16-devAndrew Waterman26-9/+515
Add support for BF16 extensions
2023-06-02Merge pull request #1372 from plctlab/plct-cmmv-fixAndrew Waterman1-2/+14
Fix bugs in disassembling code for cm.mva01s/mvsa01 instructions
2023-06-02Merge pull request #1373 from riscv-software-src/ebreakvAndrew Waterman4-12/+20
dscr.ebreakh is now dcsr.ebreakv[su]
2023-06-02Fix bugs in disassembling code for cm.mva01s/mvsa01 instructions. (Resolved ↵Weiwei Li1-2/+14
issue #1370)
2023-06-01dscr.ebreakh is now dcsr.ebreakv[su]Tim Newsome4-12/+20
This change was made ages ago in the spec. I did not actually test that the new privilege checks in ebreak and c.ebreak are correct, but all the existing debug tests still pass.
2023-05-29Add BF16 extensions to README.mdWeiwei Li1-0/+3
2023-05-29Add dsasm support for BF16 extensionsWeiwei Li1-2/+20
2023-05-29Add flh/fsh/fmv_h_x/fmv_x_h instructions to Zvfbfmin/Zvfbfwma extensionsWeiwei Li6-4/+9
2023-05-29Add support for new instructions of Zvfbfwma extensionWeiwei Li4-0/+69
2023-05-29Add support for new instructions of Zvfbfmin extensionWeiwei Li4-0/+37
2023-05-29Add support for new instructions of Zfbfmin extensionWeiwei Li4-2/+22
2023-05-29Update encoding.h to add instructions for BF16 extensionsWeiwei Li1-1/+22
2023-05-29Add isa string support for Zfbfmin/Zvfbfmin/ZvfbfwmaWeiwei Li2-0/+17
2023-05-29Add convertion function between binary float16 and float32 in softfloatWeiwei Li8-0/+316
2023-05-27Merge pull request #1368 from glg-rv/have_int128/0/topicJerry Zhao6-8/+16
Minor fixes (mostly related to __int128 support)
2023-05-26Merge pull request #1367 from glg-rv/move_isaligned/0/topicAndrew Waterman2-5/+4
decode_macros: move 'is_aligned' from 'v_ext_macros.h'
2023-05-26Fix check for extensionGianluca Guida1-1/+1
Calling 'extension_enabled' this early during the constructor of 'processor_t' causes SIGSEGV.
2023-05-26Use HAVE_INT128 instead of __SIZEOF_INT128__Gianluca Guida3-6/+6
Make sure that the configure decision on 128-bit is consistent during compilation. Also move uint128_t definition.
2023-05-26configure.h: Add HAVE_INT128Gianluca Guida3-1/+9
Modify configure.ac to generate a header that expose the support for 128-bit integers.
2023-05-26decode_macros: move 'is_aligned' from 'v_ext_macros.h'Gianluca Guida2-5/+4
2023-05-25Merge pull request #1366 from riscv-software-src/fix-1365Andrew Waterman8-63/+55
Implement dcsr.v and make DRET use it
2023-05-25Refactor set_privilege to subsume set_virtAndrew Waterman6-38/+12
This cleans up the code and avoids bugs like #1365.
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