| Age | Commit message (Collapse) | Author | Files | Lines |
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Change disasm for vset{i}vli with reserved vtypes to display the reserved bits
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Currently there is a bug with the disassembly when vsetivli/vsetvli have invalid vtypes (with reserved bits set). Spike correctly detects this and sets vill, but the disassembler integrated into spike ignores those bits being set and prints the instruction as if they weren't. This makes debugging harder, it looks like an otherwise valid vtype was being rejected and can lead down debugging paths like thinking the vector unit is configured incorrectly.
This commit changes the behaviour so that if these reserved bits are set, it prints out the hex value of the vtype. This is understood by the assembler.
GCC disassembler prints out the decimal value of the vtype in this case, I think that hex value is clearer but I can change it if desired.
Signed-off-by: Brendan Sweeney <brs@eecs.berkeley.edu>
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Hit multiple icount triggers with different actions
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action=debug
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detect_icount_fire() and detect_icount_decrement()
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Attempt to fix Mac OS CI
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Signed-off-by: viktoryou <143797577+viktoryou@users.noreply.github.com>
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fix bf16 nanboxed access
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assume
0x0000_0000_0000_7d2d at 0x8000_0000
a0 = 0x8000_0000
fld ft0, 0(a0) <- load 0x0000_0000_0000_7d2d to ft0,
it is invalid Nanboxed
fcvt.s.bf16 ft1, ft0 <- read bf16 from ft0. it should be
0x7fc0 (bf16 QNaN) but not 0x7e00 (f16 QNaN)
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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update model_test.h: set_msw/clear_msw/set_mtimer/clear_mtimer
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fdt: Install header files `fdt.h` and `libfdt_env.h` as needed by `libfdt.h`
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Include cerrno in fesvr/elfloader.cc
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It caused compile error "use of undeclared identifier 'errno'" at line 26 and 33.
I Add #include <cerrno> in fesvr/elfloader.cc to fix error and compile successfully.
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Rename *envcfg.HADE to *envcfg.ADUE
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update set_msw/clear_msw/set_mtimer/clear_mtimer
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Added ifndef to clint addresses instead of hard-coding
Added clear_msw and clear mtimer
Tested against Sail/isa-sim with new proposed Smclint/Ssclint arch-tests
https://github.com/riscv-non-isa/riscv-arch-test/pull/372
Building a baseline of interrupt tests that changes to SAIL/isa-sim can be tested against when other interrupt extensions are added.
Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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triggers: fix textra.sbytemask
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Add Smcntrpmf support
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If Smcntrpmf is enabled, mcycle / minstret increment only if counting
for the privilege level isn't inhibited in mcyclecfg / minstretcfg.
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This tracks whether the privilege / virtual mode was changed by the
execution of the current instruction.
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Ignore corresponding bytes to the scontext and textra.svalue.
Cast 0xff to reg_t for the 34-bit textra64.svalue.
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Add Smcsrind / Sscsrind support
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Legalize xenvcfg.CBIE
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The value 2 of henvcfg.CBIE is reserved. This commit legalizes it to 0.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
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The value 2 of senvcfg.CBIE is reserved. This commit legalizes it to 0.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
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The value 2 of menvcfg.CBIE is reserved. This commit legalizes it to 0
by adding a specialized class envcfg_csr_t.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
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Fix compilation warning in riscv/execute.cc
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Make methods of `mem_t` virtual to allow overriding
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../riscv/execute.cc: In function ‘void commit_log_print_insn(processor_t*, reg_t, insn_t)’:
../riscv/execute.cc:132:16: warning: ‘prefix’ may be used uninitialized [-Wmaybe-uninitialized]
132 | fprintf(log_file, " %c%-2d ", prefix, rd);
| ~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../riscv/execute.cc:88:10: note: ‘prefix’ was declared here
88 | char prefix;
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This change allows to create custom implementations of `abstract_mem_t`
and inject them when constructing `sim_t`. The current `mem_t`
implementation remains unchanged.
Fixes #1408.
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This adds the following CSRs:
miselect (0x350), mireg (0x351), mireg2/3 (0x352, 0x353),
mireg4-6 (0x355 - 0x357), siselect (0x150), sireg (0x151),
sireg2/3 (0x152, 0x153), sireg4-6 (0x155 - 0x157), vsiselect (0x250),
vsireg (0x251), mireg2/3 (0x252, 0x253), vsireg4-6 (0x255 - 0x257).
Presently, attempts to read / write from ireg? registers will fail, and
future extensions will provide proxy CSR mappings for the respective
?ireg CSRs.
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mcontrol/mcontrol6 on CBO
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The mcontrol/mcontrol6 store address before has a higher priority over page
faults and access faults. Thus, trigger checking should before the translate().
This commit checks all address of the cache block.
Reference: Debug spec 1.0, 5.5.3 Cache Operations
Reference: CMO spec 1.0.1, 2.5.4 Breakpoint Exceptions and Debug Mode Entry
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mmu: fetch instruction bytes in ascending order
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Fetching instruction bytes in descending order would result in
wrong xtval update values.
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The tval should capture the effective address on an (trigger) exception.
Reference: https://github.com/riscv/riscv-CMOs/issues/55
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Add all symbols from extension.o to spike main
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The --extension feature requires that all symbols in extension.o
be available when the libraries are dynamically loaded by dlopen.
Prepending extension.o to the linker command adds the otherwise
omitted symbols to spike's dynamic symbol table.
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