diff options
Diffstat (limited to 'riscv/insns')
40 files changed, 163 insertions, 8 deletions
diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h index 8743266..6f2c8f4 100644 --- a/riscv/insns/c_fsd.h +++ b/riscv/insns/c_fsd.h @@ -1,4 +1,4 @@ require_extension('C'); require_extension('D'); require_fp; -MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v); +MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v[0]); diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h index f62f8ff..27b9331 100644 --- a/riscv/insns/c_fsdsp.h +++ b/riscv/insns/c_fsdsp.h @@ -1,4 +1,4 @@ require_extension('C'); require_extension('D'); require_fp; -MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v); +MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v[0]); diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h index b924a46..7085822 100644 --- a/riscv/insns/c_fsw.h +++ b/riscv/insns/c_fsw.h @@ -2,7 +2,7 @@ require_extension('C'); if (xlen == 32) { require_extension('F'); require_fp; - MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v); + MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); } else { // c.sd MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); } diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h index 011de55..c5a003f 100644 --- a/riscv/insns/c_fswsp.h +++ b/riscv/insns/c_fswsp.h @@ -2,7 +2,7 @@ require_extension('C'); if (xlen == 32) { require_extension('F'); require_fp; - MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v); + MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]); } else { // c.sdsp MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2); } diff --git a/riscv/insns/fadd_q.h b/riscv/insns/fadd_q.h new file mode 100644 index 0000000..1139a74 --- /dev/null +++ b/riscv/insns/fadd_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_add(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/fclass_q.h b/riscv/insns/fclass_q.h new file mode 100644 index 0000000..5330758 --- /dev/null +++ b/riscv/insns/fclass_q.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_RD(f128_classify(f128(FRS1))); diff --git a/riscv/insns/fcvt_d_q.h b/riscv/insns/fcvt_d_q.h new file mode 100644 index 0000000..b50a43d --- /dev/null +++ b/riscv/insns/fcvt_d_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_to_f64(f128(FRS1))); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_q.h b/riscv/insns/fcvt_l_q.h new file mode 100644 index 0000000..b28bca2 --- /dev/null +++ b/riscv/insns/fcvt_l_q.h @@ -0,0 +1,6 @@ +require_extension('Q'); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f128_to_i64(f128(FRS1), RM, true)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_q.h b/riscv/insns/fcvt_lu_q.h new file mode 100644 index 0000000..8c5be7c --- /dev/null +++ b/riscv/insns/fcvt_lu_q.h @@ -0,0 +1,6 @@ +require_extension('Q'); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f128_to_ui64(f128(FRS1), RM, true)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_q_d.h b/riscv/insns/fcvt_q_d.h new file mode 100644 index 0000000..c2437b1 --- /dev/null +++ b/riscv/insns/fcvt_q_d.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f64_to_f128(f64(FRS1))); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_q_l.h b/riscv/insns/fcvt_q_l.h new file mode 100644 index 0000000..f1f45ca --- /dev/null +++ b/riscv/insns/fcvt_q_l.h @@ -0,0 +1,6 @@ +require_extension('Q'); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(i64_to_f128(RS1)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_q_lu.h b/riscv/insns/fcvt_q_lu.h new file mode 100644 index 0000000..850212e --- /dev/null +++ b/riscv/insns/fcvt_q_lu.h @@ -0,0 +1,6 @@ +require_extension('Q'); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(ui64_to_f128(RS1)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_q_s.h b/riscv/insns/fcvt_q_s.h new file mode 100644 index 0000000..79e6bb6 --- /dev/null +++ b/riscv/insns/fcvt_q_s.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f32_to_f128(f32(FRS1))); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_q_w.h b/riscv/insns/fcvt_q_w.h new file mode 100644 index 0000000..fb83f15 --- /dev/null +++ b/riscv/insns/fcvt_q_w.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(i32_to_f128((int32_t)RS1)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_q_wu.h b/riscv/insns/fcvt_q_wu.h new file mode 100644 index 0000000..7c2ae97 --- /dev/null +++ b/riscv/insns/fcvt_q_wu.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(ui32_to_f128((uint32_t)RS1)); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_q.h b/riscv/insns/fcvt_s_q.h new file mode 100644 index 0000000..b0f118e --- /dev/null +++ b/riscv/insns/fcvt_s_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_to_f32(f128(FRS1))); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_q.h b/riscv/insns/fcvt_w_q.h new file mode 100644 index 0000000..e10bafc --- /dev/null +++ b/riscv/insns/fcvt_w_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f128_to_i32(f128(FRS1), RM, true))); +set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_q.h b/riscv/insns/fcvt_wu_q.h new file mode 100644 index 0000000..c391dc8 --- /dev/null +++ b/riscv/insns/fcvt_wu_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f128_to_ui32(f128(FRS1), RM, true))); +set_fp_exceptions; diff --git a/riscv/insns/fdiv_q.h b/riscv/insns/fdiv_q.h new file mode 100644 index 0000000..2204831 --- /dev/null +++ b/riscv/insns/fdiv_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_div(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/feq_q.h b/riscv/insns/feq_q.h new file mode 100644 index 0000000..cee2da9 --- /dev/null +++ b/riscv/insns/feq_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_fp; +WRITE_RD(f128_eq(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/fle_q.h b/riscv/insns/fle_q.h new file mode 100644 index 0000000..8368af9 --- /dev/null +++ b/riscv/insns/fle_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_fp; +WRITE_RD(f128_le(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/flq.h b/riscv/insns/flq.h new file mode 100644 index 0000000..81d225c --- /dev/null +++ b/riscv/insns/flq.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_FRD(MMU.load_float128(RS1 + insn.i_imm())); diff --git a/riscv/insns/flt_q.h b/riscv/insns/flt_q.h new file mode 100644 index 0000000..c452141 --- /dev/null +++ b/riscv/insns/flt_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_fp; +WRITE_RD(f128_lt(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/fmadd_q.h b/riscv/insns/fmadd_q.h new file mode 100644 index 0000000..882dfc1 --- /dev/null +++ b/riscv/insns/fmadd_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128(FRS1), f128(FRS2), f128(FRS3))); +set_fp_exceptions; diff --git a/riscv/insns/fmax_q.h b/riscv/insns/fmax_q.h new file mode 100644 index 0000000..719e6d0 --- /dev/null +++ b/riscv/insns/fmax_q.h @@ -0,0 +1,8 @@ +require_extension('Q'); +require_fp; +bool greater = f128_lt_quiet(f128(FRS2), f128(FRS1)) || + (f128_eq(f128(FRS2), f128(FRS1)) && (f128(FRS2).v[1] & F64_SIGN)); +WRITE_FRD(greater || isNaNF128(f128(FRS2)) ? FRS1 : FRS2); +if (isNaNF128(f128(FRS1)) && isNaNF128(f128(FRS2))) + WRITE_FRD(f128(defaultNaNF128())); +set_fp_exceptions; diff --git a/riscv/insns/fmin_q.h b/riscv/insns/fmin_q.h new file mode 100644 index 0000000..675c7fd --- /dev/null +++ b/riscv/insns/fmin_q.h @@ -0,0 +1,8 @@ +require_extension('Q'); +require_fp; +bool less = f128_lt_quiet(f128(FRS1), f128(FRS2)) || + (f128_eq(f128(FRS1), f128(FRS2)) && (f128(FRS1).v[1] & F64_SIGN)); +WRITE_FRD(less || isNaNF128(f128(FRS2)) ? FRS1 : FRS2); +if (isNaNF128(f128(FRS1)) && isNaNF128(f128(FRS2))) + WRITE_FRD(f128(defaultNaNF128())); +set_fp_exceptions; diff --git a/riscv/insns/fmsub_q.h b/riscv/insns/fmsub_q.h new file mode 100644 index 0000000..1bb96c2 --- /dev/null +++ b/riscv/insns/fmsub_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128(FRS1), f128(FRS2), f128_negate(f128(FRS3)))); +set_fp_exceptions; diff --git a/riscv/insns/fmul_q.h b/riscv/insns/fmul_q.h new file mode 100644 index 0000000..66f5a05 --- /dev/null +++ b/riscv/insns/fmul_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mul(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h index da8e72a..e1a23f4 100644 --- a/riscv/insns/fmv_x_d.h +++ b/riscv/insns/fmv_x_d.h @@ -1,4 +1,4 @@ require_extension('D'); require_rv64; require_fp; -WRITE_RD(FRS1.v); +WRITE_RD(FRS1.v[0]); diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h index b722479..6754f86 100644 --- a/riscv/insns/fmv_x_w.h +++ b/riscv/insns/fmv_x_w.h @@ -1,3 +1,3 @@ require_extension('F'); require_fp; -WRITE_RD(sext32(FRS1.v)); +WRITE_RD(sext32(FRS1.v[0])); diff --git a/riscv/insns/fnmadd_q.h b/riscv/insns/fnmadd_q.h new file mode 100644 index 0000000..a36ce18 --- /dev/null +++ b/riscv/insns/fnmadd_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128_negate(f128(FRS1)), f128(FRS2), f128_negate(f128(FRS3)))); +set_fp_exceptions; diff --git a/riscv/insns/fnmsub_q.h b/riscv/insns/fnmsub_q.h new file mode 100644 index 0000000..130b4ce --- /dev/null +++ b/riscv/insns/fnmsub_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128_negate(f128(FRS1)), f128(FRS2), f128(FRS3))); +set_fp_exceptions; diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h index 679cc95..38c702b 100644 --- a/riscv/insns/fsd.h +++ b/riscv/insns/fsd.h @@ -1,3 +1,3 @@ require_extension('D'); require_fp; -MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v); +MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v[0]); diff --git a/riscv/insns/fsgnj_q.h b/riscv/insns/fsgnj_q.h new file mode 100644 index 0000000..0b9a270 --- /dev/null +++ b/riscv/insns/fsgnj_q.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_FRD(fsgnj128(FRS1, FRS2, false, false)); diff --git a/riscv/insns/fsgnjn_q.h b/riscv/insns/fsgnjn_q.h new file mode 100644 index 0000000..38c7bbf --- /dev/null +++ b/riscv/insns/fsgnjn_q.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_FRD(fsgnj128(FRS1, FRS2, true, false)); diff --git a/riscv/insns/fsgnjx_q.h b/riscv/insns/fsgnjx_q.h new file mode 100644 index 0000000..fc86d26 --- /dev/null +++ b/riscv/insns/fsgnjx_q.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_FRD(fsgnj128(FRS1, FRS2, false, true)); diff --git a/riscv/insns/fsq.h b/riscv/insns/fsq.h new file mode 100644 index 0000000..610960e --- /dev/null +++ b/riscv/insns/fsq.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +MMU.store_float128(RS1 + insn.s_imm(), FRS2); diff --git a/riscv/insns/fsqrt_q.h b/riscv/insns/fsqrt_q.h new file mode 100644 index 0000000..6cb6ba3 --- /dev/null +++ b/riscv/insns/fsqrt_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_sqrt(f128(FRS1))); +set_fp_exceptions; diff --git a/riscv/insns/fsub_q.h b/riscv/insns/fsub_q.h new file mode 100644 index 0000000..e050e3a --- /dev/null +++ b/riscv/insns/fsub_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_sub(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h index 42fc683..8af5184 100644 --- a/riscv/insns/fsw.h +++ b/riscv/insns/fsw.h @@ -1,3 +1,3 @@ require_extension('F'); require_fp; -MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v); +MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v[0]); |