diff options
Diffstat (limited to 'riscv/disasm.cc')
| -rw-r--r-- | riscv/disasm.cc | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/riscv/disasm.cc b/riscv/disasm.cc index 57f43d7..86b70e0 100644 --- a/riscv/disasm.cc +++ b/riscv/disasm.cc @@ -438,13 +438,6 @@ disassembler::disassembler() #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, frs1_reg) #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, frd_reg, xrs1_reg) - #define DEFINE_RS1(code) DISASM_INSN(#code, code, 0, xrs1_reg) - #define DEFINE_RS1_RS2(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg) - #define DEFINE_VEC_XMEM(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg) - #define DEFINE_VEC_XMEMST(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg, xrs2_reg) - #define DEFINE_VEC_FMEM(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg) - #define DEFINE_VEC_FMEMST(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg, xrs2_reg) - DEFINE_XLOAD(lb) DEFINE_XLOAD(lbu) DEFINE_XLOAD(lh) @@ -571,17 +564,6 @@ disassembler::disassembler() add_insn(new disasm_insn_t("clearpcr", match_clearpcr, mask_clearpcr, xrd_reg, pcr_reg, imm)); DEFINE_NOARG(eret) - DEFINE_RS1(vxcptsave); - DEFINE_RS1(vxcptrestore); - DEFINE_NOARG(vxcptkill); - - DEFINE_RS1(vxcptevac); - DEFINE_NOARG(vxcpthold); - DEFINE_RS1_RS2(venqcmd); - DEFINE_RS1_RS2(venqimm1); - DEFINE_RS1_RS2(venqimm2); - DEFINE_RS1_RS2(venqcnt); - DEFINE_FRTYPE(fadd_s); DEFINE_FRTYPE(fsub_s); DEFINE_FRTYPE(fmul_s); @@ -646,58 +628,6 @@ disassembler::disassembler() add_insn(new disasm_insn_t("mtfsr", match_mtfsr, mask_mtfsr, xrd_reg, xrs1_reg)); DEFINE_DTYPE(mffsr); - DEFINE_VEC_XMEM(vld); - DEFINE_VEC_XMEM(vlw); - DEFINE_VEC_XMEM(vlwu); - DEFINE_VEC_XMEM(vlh); - DEFINE_VEC_XMEM(vlhu); - DEFINE_VEC_XMEM(vlb); - DEFINE_VEC_XMEM(vlbu); - DEFINE_VEC_FMEM(vfld); - DEFINE_VEC_FMEM(vflw); - DEFINE_VEC_XMEMST(vlstd); - DEFINE_VEC_XMEMST(vlstw); - DEFINE_VEC_XMEMST(vlstwu); - DEFINE_VEC_XMEMST(vlsth); - DEFINE_VEC_XMEMST(vlsthu); - DEFINE_VEC_XMEMST(vlstb); - DEFINE_VEC_XMEMST(vlstbu); - DEFINE_VEC_FMEMST(vflstd); - DEFINE_VEC_FMEMST(vflstw); - - DEFINE_VEC_XMEM(vsd); - DEFINE_VEC_XMEM(vsw); - DEFINE_VEC_XMEM(vsh); - DEFINE_VEC_XMEM(vsb); - DEFINE_VEC_FMEM(vfsd); - DEFINE_VEC_FMEM(vfsw); - DEFINE_VEC_XMEMST(vsstd); - DEFINE_VEC_XMEMST(vsstw); - DEFINE_VEC_XMEMST(vssth); - DEFINE_VEC_XMEMST(vsstb); - DEFINE_VEC_FMEMST(vfsstd); - DEFINE_VEC_FMEMST(vfsstw); - - DISASM_INSN("vmvv", vmvv, 0, vxrd_reg, vxrs1_reg); - DISASM_INSN("vmsv", vmsv, 0, vxrd_reg, xrs1_reg); - DISASM_INSN("vmst", vmst, 0, vxrd_reg, xrs1_reg, xrs2_reg); - DISASM_INSN("vmts", vmts, 0, xrd_reg, vxrs1_reg, xrs2_reg); - DISASM_INSN("vfmvv", vfmvv, 0, vfrd_reg, vfrs1_reg); - DISASM_INSN("vfmsv", vfmsv, 0, vfrd_reg, frs1_reg); - DISASM_INSN("vfmst", vfmst, 0, vfrd_reg, frs1_reg, frs2_reg); - DISASM_INSN("vfmts", vfmts, 0, frd_reg, vfrs1_reg, frs2_reg); - - DEFINE_RS1_RS2(vvcfg); - DEFINE_RS1_RS2(vtcfg); - - DISASM_INSN("vvcfgivl", vvcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg); - DISASM_INSN("vtcfgivl", vtcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg); - DISASM_INSN("vsetvl", vsetvl, 0, xrd_reg, xrs1_reg); - DISASM_INSN("vf", vf, 0, xrs1_reg, imm); - - DEFINE_NOARG(fence_v_l); - DEFINE_NOARG(fence_v_g); - // provide a default disassembly for all instructions as a fallback #define DECLARE_INSN(code, match, mask) \ add_insn(new disasm_insn_t(#code " (args unknown)", match, mask)); |