diff options
-rw-r--r-- | riscv/mmu.cc | 11 | ||||
-rw-r--r-- | riscv/mmu.h | 8 |
2 files changed, 4 insertions, 15 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index eee83bd..16e00d7 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -150,16 +150,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate if (require_alignment) { load_reserved_address_misaligned(addr); } else { - reg_t value = misaligned_load(addr, len, xlate_flags); - for (size_t i = 0; i < len; i++) { - if (target_big_endian) { - bytes[len - i - 1] = value & 0xff; - } else { - bytes[i] = value & 0xff; - } - value >>= 8; - } - return; + return misaligned_load(addr, len, bytes, xlate_flags); } } diff --git a/riscv/mmu.h b/riscv/mmu.h index dd08372..b011287 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -52,13 +52,11 @@ public: #define RISCV_XLATE_VIRT (1U << 0) #define RISCV_XLATE_VIRT_HLVX (1U << 1) - inline reg_t misaligned_load(reg_t addr, size_t size, uint32_t xlate_flags) + inline void misaligned_load(reg_t addr, reg_t len, uint8_t *bytes, uint32_t xlate_flags) { #ifdef RISCV_ENABLE_MISALIGNED - reg_t res = 0; - for (size_t i = 0; i < size; i++) - res += (reg_t)load_uint8(addr + (target_big_endian? size-1-i : i)) << (i * 8); - return res; + for (size_t i = 0; i < len; i++) + bytes[i] = load_uint8(addr + i); #else bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); throw trap_load_address_misaligned(gva, addr, 0, 0); |