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author | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2022-12-29 15:49:27 +0300 |
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committer | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2023-01-09 19:16:44 +0300 |
commit | f403cb9e542155787b862d726ba334e0d0895c74 (patch) | |
tree | e9a186b4dcbd2f2fae2e2de1794873a35759d708 /spike_main | |
parent | fcf61f000804a05bc06d708152c15a527c6461cb (diff) | |
download | riscv-isa-sim-f403cb9e542155787b862d726ba334e0d0895c74.zip riscv-isa-sim-f403cb9e542155787b862d726ba334e0d0895c74.tar.gz riscv-isa-sim-f403cb9e542155787b862d726ba334e0d0895c74.tar.bz2 |
simplify check_mem_overlap by utilizing get_inclusive_end of mem_cfg_t
Diffstat (limited to 'spike_main')
-rw-r--r-- | spike_main/spike.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 5a3d995..b3cffae 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -128,10 +128,7 @@ bool sort_mem_region(const mem_cfg_t &a, const mem_cfg_t &b) static bool check_mem_overlap(const mem_cfg_t& L, const mem_cfg_t& R) { - const auto L_end = L.get_base() + L.get_size() - 1; - const auto R_end = R.get_base() + R.get_size() - 1; - - return std::max(L.get_base(), R.get_base()) <= std::min(L_end, R_end); + return std::max(L.get_base(), R.get_base()) <= std::min(L.get_inclusive_end(), R.get_inclusive_end()); } static mem_cfg_t merge_mem_regions(const mem_cfg_t& L, const mem_cfg_t& R) |