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author | Andrew Waterman <andrew@sifive.com> | 2022-10-20 12:46:40 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-20 12:54:47 -0700 |
commit | da2164847258855bb8863f5aa97945da8603642d (patch) | |
tree | 7f812d15812cabae05851b5b13c1b76dde4a55b2 /spike_main | |
parent | e8340aedc84cc9daee1f66e718a4b4a887cb8749 (diff) | |
download | riscv-isa-sim-da2164847258855bb8863f5aa97945da8603642d.zip riscv-isa-sim-da2164847258855bb8863f5aa97945da8603642d.tar.gz riscv-isa-sim-da2164847258855bb8863f5aa97945da8603642d.tar.bz2 |
Set 16..4096-byte bound on cache-block size
16 B suffices to subsume all aligned accesses (including the Q extension).
Spike does not actually rely on this property, but in some real systems,
it is impractical to guarantee atomicity across cache lines.
4096 B suffices to prevent cache lines from spanning pages (which would
require multiple TLB accesses). This one is a bug fix, since we were
not performing multiple TLB accesses in this case.
Diffstat (limited to 'spike_main')
-rw-r--r-- | spike_main/spike.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 933f626..20afac9 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -411,8 +411,11 @@ int main(int argc, char** argv) }); parser.option(0, "blocksz", 1, [&](const char* s){ blocksz = strtoull(s, 0, 0); - if (((blocksz & (blocksz - 1))) != 0) { - fprintf(stderr, "--blocksz should be power of 2\n"); + const unsigned min_blocksz = 16; + const unsigned max_blocksz = PGSIZE; + if (blocksz < min_blocksz || blocksz > max_blocksz || ((blocksz & (blocksz - 1))) != 0) { + fprintf(stderr, "--blocksz must be a power of 2 between %u and %u\n", + min_blocksz, max_blocksz); exit(-1); } }); |