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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-25 21:33:49 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-31 00:44:35 -0700 |
| commit | c9da2943328acf74f58812f1bf29cfc4091dc4cd (patch) | |
| tree | 195c92e357786fa97d62326332eeb209cce7bda2 /spike_main | |
| parent | eceda60356a435dfac2c5573badf0144f4c7f146 (diff) | |
| download | riscv-isa-sim-c9da2943328acf74f58812f1bf29cfc4091dc4cd.zip riscv-isa-sim-c9da2943328acf74f58812f1bf29cfc4091dc4cd.tar.gz riscv-isa-sim-c9da2943328acf74f58812f1bf29cfc4091dc4cd.tar.bz2 | |
rvv: add reciprocal instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'spike_main')
| -rw-r--r-- | spike_main/disasm.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 2736e80..4477e19 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -1136,6 +1136,8 @@ disassembler_t::disassembler_t(int xlen) //vfunary1 DISASM_INSN("vfsqrt.v", vfsqrt_v, 0, {&vd, &vs2, &opt, &vm}); + DISASM_INSN("vfrsqrte7.v", vfrsqrte7_v, 0, {&vd, &vs2, &opt, &vm}); + DISASM_INSN("vfrece7.v", vfrece7_v, 0, {&vd, &vs2, &opt, &vm}); DISASM_INSN("vfclass.v", vfclass_v, 0, {&vd, &vs2, &opt, &vm}); DISASM_OPIV_VF_INSN(vfmul); |