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author | Andrew Waterman <andrew@sifive.com> | 2020-06-16 22:11:30 -0700 |
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committer | GitHub <noreply@github.com> | 2020-06-16 22:11:30 -0700 |
commit | 960274cda20af7303fdf8109e27d9720395ae21f (patch) | |
tree | c6891384ddc1855c049630c82d8e2a690ca163d2 /spike_main | |
parent | 3369e92602c090b1a0744145301c5abb5f2ece33 (diff) | |
parent | 0ea56186d527433c21cf76e2d2a6a53a8d9695dc (diff) | |
download | riscv-isa-sim-960274cda20af7303fdf8109e27d9720395ae21f.zip riscv-isa-sim-960274cda20af7303fdf8109e27d9720395ae21f.tar.gz riscv-isa-sim-960274cda20af7303fdf8109e27d9720395ae21f.tar.bz2 |
Merge pull request #490 from chihminchao/rvv-fix-2020-06-17
Rvv fix 2020 06 17
Diffstat (limited to 'spike_main')
-rw-r--r-- | spike_main/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index e163130..626d37c 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -843,7 +843,7 @@ disassembler_t::disassembler_t(int xlen) #define DISASM_OPIV_W___INSN(name, sign) \ add_insn(new disasm_insn_t(#name ".wv", match_##name##_wv, mask_##name##_wv, \ {&vd, &vs2, &vs1, &opt, &vm})); \ - add_insn(new disasm_insn_t(#name ".wx", match_##name##_wv, mask_##name##_wv, \ + add_insn(new disasm_insn_t(#name ".wx", match_##name##_wx, mask_##name##_wx, \ {&vd, &vs2, &xrs1, &opt, &vm})); #define DISASM_OPIV_M___INSN(name, sign) \ |