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| author | Andrew Waterman <andrew@sifive.com> | 2020-07-21 23:02:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-07-21 23:03:52 -0700 |
| commit | 67b7edd0270d5d074136eb45474477d15aeee725 (patch) | |
| tree | d0364e2c34c224bcef36a59b0fb0c37ba88183b0 /spike_main | |
| parent | 8d860c190640e19e0f23a21d2479b4a36d13d342 (diff) | |
| download | riscv-isa-sim-67b7edd0270d5d074136eb45474477d15aeee725.zip riscv-isa-sim-67b7edd0270d5d074136eb45474477d15aeee725.tar.gz riscv-isa-sim-67b7edd0270d5d074136eb45474477d15aeee725.tar.bz2 | |
Remove deprecated decoding of xor x0,x0,x0
Some UCB implementations once used this to represent a pipeline bubble.
But this encoding is reserved for future standard HINT use.
Resolves #503
Diffstat (limited to 'spike_main')
| -rw-r--r-- | spike_main/disasm.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 626d37c..d551062 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -489,7 +489,6 @@ disassembler_t::disassembler_t(int xlen) DEFINE_ITYPE(jalr); add_insn(new disasm_insn_t("nop", match_addi, mask_addi | mask_rd | mask_rs1 | mask_imm, {})); - add_insn(new disasm_insn_t(" - ", match_xor, mask_xor | mask_rd | mask_rs1 | mask_rs2, {})); // for machine-generated bubbles DEFINE_I0TYPE("li", addi); DEFINE_I1TYPE("mv", addi); DEFINE_ITYPE(addi); |