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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-26 20:13:31 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-31 00:44:36 -0700 |
commit | 52b3eb938079c0d91f40cfc1a733ee21dfa03de7 (patch) | |
tree | 058dc2bbd90803085f28534933aaf9a04fe1e342 /spike_main | |
parent | 6f7b46f71fd1893e773791900d78c6ca05db712d (diff) | |
download | riscv-isa-sim-52b3eb938079c0d91f40cfc1a733ee21dfa03de7.zip riscv-isa-sim-52b3eb938079c0d91f40cfc1a733ee21dfa03de7.tar.gz riscv-isa-sim-52b3eb938079c0d91f40cfc1a733ee21dfa03de7.tar.bz2 |
rvv: disasm: fix whole load
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'spike_main')
-rw-r--r-- | spike_main/disasm.cc | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 4477e19..02be637 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -795,17 +795,24 @@ disassembler_t::disassembler_t(int xlen) } } + //handle whole register load + if (elt >= 4) + continue; + const custom_fmt_t template_insn2[] = { {match_vl1re8_v, mask_vl1re8_v, "vl%dre%d.v", v_ld_unit}, }; - for (reg_t i = 0, nf = 7; nf < 4; i++, nf >>= 1) { - for (auto item : template_insn) { + for (reg_t i = 0, nf = 7; i < 4; i++, nf >>= 1) { + for (auto item : template_insn2) { const reg_t match_nf = nf << 29; char buf[128]; sprintf(buf, item.fmt, nf + 1, 8 << elt); add_insn(new disasm_insn_t( - buf, item.match | match_nf, item.mask | mask_nf, item.arg + buf, + item.match | match_nf | elt_map[elt], + item.mask | mask_nf, + item.arg )); } } |