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| author | Eric Gouriou <ego@rivosinc.com> | 2023-06-01 18:07:22 -0700 |
|---|---|---|
| committer | Eric Gouriou <ego@rivosinc.com> | 2023-06-19 14:30:34 -0700 |
| commit | fbd4ca2eef884b6835e848d761b3e375a66fc47a (patch) | |
| tree | 6fff44dce7b7a5adc93d10886cd52929f1a2c32e /softfloat/s_mul64To128.c | |
| parent | d633af2b180391b6f73f84f56d8b305a3af7c152 (diff) | |
| download | riscv-isa-sim-fbd4ca2eef884b6835e848d761b3e375a66fc47a.zip riscv-isa-sim-fbd4ca2eef884b6835e848d761b3e375a66fc47a.tar.gz riscv-isa-sim-fbd4ca2eef884b6835e848d761b3e375a66fc47a.tar.bz2 | |
Zvk: Implement Zvkg, Vector GCM/GMAC instruction
Implement the proposed instruction in Zvkg, vghmac.vv,
Vector Carryless Multiply Accumulate over GHASH Galois-Field.
The instruction performs one step of GHASH routine as described
in "NIST Special Publication 800-38D" a.k.a the AES-GCM specification.
The logic was written to closely track the pseudo-code
in the Zvk specification.
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Co-authored-by: Kornel Duleba <mindal@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Diffstat (limited to 'softfloat/s_mul64To128.c')
0 files changed, 0 insertions, 0 deletions