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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-06 18:00:18 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-08 15:05:52 -0700 |
| commit | d36c66176521639f0d30d67b9232e1995c3c3385 (patch) | |
| tree | 44c0b28fc1ca8ac6f2a2edb49cc5ea7cfd75d87f /riscv | |
| parent | d9bef8871f9e59e7cab17f3a31c054af1bf7f047 (diff) | |
| download | riscv-isa-sim-d36c66176521639f0d30d67b9232e1995c3c3385.zip riscv-isa-sim-d36c66176521639f0d30d67b9232e1995c3c3385.tar.gz riscv-isa-sim-d36c66176521639f0d30d67b9232e1995c3c3385.tar.bz2 | |
Rename MTFSR/MFFSR to FSSR/FRSR
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/disasm.cc | 6 | ||||
| -rw-r--r-- | riscv/insns/frsr.h (renamed from riscv/insns/mffsr.h) | 0 | ||||
| -rw-r--r-- | riscv/insns/fssr.h (renamed from riscv/insns/mtfsr.h) | 0 | ||||
| -rw-r--r-- | riscv/opcodes.h | 4 |
4 files changed, 5 insertions, 5 deletions
diff --git a/riscv/disasm.cc b/riscv/disasm.cc index 570ed65..105df75 100644 --- a/riscv/disasm.cc +++ b/riscv/disasm.cc @@ -624,9 +624,9 @@ disassembler::disassembler() DEFINE_FXTYPE(flt_d); DEFINE_FXTYPE(fle_d); - add_insn(new disasm_insn_t("mtfsr", match_mtfsr, mask_mtfsr | mask_rd, xrs1_reg)); - add_insn(new disasm_insn_t("mtfsr", match_mtfsr, mask_mtfsr, xrd_reg, xrs1_reg)); - DEFINE_DTYPE(mffsr); + add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr | mask_rd, xrs1_reg)); + add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr, xrd_reg, xrs1_reg)); + DEFINE_DTYPE(frsr); // provide a default disassembly for all instructions as a fallback #define DECLARE_INSN(code, match, mask) \ diff --git a/riscv/insns/mffsr.h b/riscv/insns/frsr.h index 29debc4..29debc4 100644 --- a/riscv/insns/mffsr.h +++ b/riscv/insns/frsr.h diff --git a/riscv/insns/mtfsr.h b/riscv/insns/fssr.h index cc6f9ea..cc6f9ea 100644 --- a/riscv/insns/mtfsr.h +++ b/riscv/insns/fssr.h diff --git a/riscv/opcodes.h b/riscv/opcodes.h index 90565e0..5e366cd 100644 --- a/riscv/opcodes.h +++ b/riscv/opcodes.h @@ -9,6 +9,7 @@ DECLARE_INSN(lb, 0x3, 0x3ff) DECLARE_INSN(fcvt_s_wu, 0xf053, 0x3ff1ff) DECLARE_INSN(fcvt_d_l, 0xc0d3, 0x3ff1ff) DECLARE_INSN(lh, 0x83, 0x3ff) +DECLARE_INSN(frsr, 0x1d053, 0x7ffffff) DECLARE_INSN(fcvt_d_w, 0xe0d3, 0x3ff1ff) DECLARE_INSN(lw, 0x103, 0x3ff) DECLARE_INSN(add, 0x33, 0x1ffff) @@ -38,7 +39,6 @@ DECLARE_INSN(fnmsub_s, 0x4b, 0x1ff) DECLARE_INSN(fcvt_l_s, 0x8053, 0x3ff1ff) DECLARE_INSN(fle_s, 0x17053, 0x1ffff) DECLARE_INSN(fence_v_l, 0x22f, 0x3ff) -DECLARE_INSN(mffsr, 0x1d053, 0x7ffffff) DECLARE_INSN(fdiv_s, 0x3053, 0x1f1ff) DECLARE_INSN(fle_d, 0x170d3, 0x1ffff) DECLARE_INSN(fence_i, 0xaf, 0x3ff) @@ -49,7 +49,6 @@ DECLARE_INSN(xor, 0x233, 0x1ffff) DECLARE_INSN(sub, 0x10033, 0x1ffff) DECLARE_INSN(eret, 0x273, 0xffffffff) DECLARE_INSN(blt, 0x263, 0x3ff) -DECLARE_INSN(mtfsr, 0x1f053, 0x3fffff) DECLARE_INSN(sc_w, 0x1052b, 0x1ffff) DECLARE_INSN(rem, 0x733, 0x1ffff) DECLARE_INSN(srliw, 0x29b, 0x3f83ff) @@ -129,6 +128,7 @@ DECLARE_INSN(amomax_w, 0x152b, 0x1ffff) DECLARE_INSN(fsgnj_d, 0x50d3, 0x1ffff) DECLARE_INSN(mulhu, 0x5b3, 0x1ffff) DECLARE_INSN(fence_v_g, 0x2af, 0x3ff) +DECLARE_INSN(fssr, 0x1f053, 0x3fffff) DECLARE_INSN(setpcr, 0x173, 0x3ff) DECLARE_INSN(fcvt_lu_s, 0x9053, 0x3ff1ff) DECLARE_INSN(fcvt_s_l, 0xc053, 0x3ff1ff) |