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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-04-25 16:36:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-04-25 16:36:25 -0700 |
| commit | b363c55cfe345764e5aa5e9be2169b546837c69a (patch) | |
| tree | c611ad2fc2d972f7f05e040cba6bc91ea3300cee /riscv | |
| parent | 14cfc50a602a38e8d428f73526d8e6bcbdf59793 (diff) | |
| download | riscv-isa-sim-b363c55cfe345764e5aa5e9be2169b546837c69a.zip riscv-isa-sim-b363c55cfe345764e5aa5e9be2169b546837c69a.tar.gz riscv-isa-sim-b363c55cfe345764e5aa5e9be2169b546837c69a.tar.bz2 | |
use inttypes macros to print uint64_t
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/interactive.cc | 5 | ||||
| -rw-r--r-- | riscv/processor.cc | 15 |
2 files changed, 11 insertions, 9 deletions
diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 98e4bb9..da8e5bd 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -6,6 +6,7 @@ #include <map> #include <iostream> #include <climits> +#include <cinttypes> #include <assert.h> #include <stdlib.h> #include <unistd.h> @@ -160,7 +161,7 @@ reg_t sim_t::get_freg(const std::vector<std::string>& args) void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) { - printf("0x%016llx\n",(unsigned long long)get_reg(args)); + printf("0x%016" PRIx64 "\n", get_reg(args)); } union fpr @@ -225,7 +226,7 @@ reg_t sim_t::get_mem(const std::vector<std::string>& args) void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::string>& args) { - printf("0x%016llx\n",(unsigned long long)get_mem(args)); + printf("0x%016" PRIx64 "\n", get_mem(args)); } void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args) diff --git a/riscv/processor.cc b/riscv/processor.cc index e124820..74a98a8 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -5,11 +5,12 @@ #include "config.h" #include "sim.h" #include "disasm.h" -#include <inttypes.h> +#include <cinttypes> #include <cmath> #include <cstdlib> #include <iostream> #include <assert.h> +#include <limits.h> processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) : sim(*_sim), mmu(*_mmu), id(_id), utidx(0) @@ -176,11 +177,11 @@ void processor_t::take_trap(reg_t t, bool noisy) if(noisy) { if ((sreg_t)t < 0) - printf("core %3d: interrupt %lld, pc 0x%016llx\n", - id, (long long)(t << 1 >> 1), (unsigned long long)pc); + printf("core %3d: interrupt %d, epc 0x%016" PRIx64 "\n", + id, uint8_t(t), pc); else - printf("core %3d: trap %s, pc 0x%016llx\n", - id, trap_name(trap_t(t)), (unsigned long long)pc); + printf("core %3d: trap %s, epc 0x%016" PRIx64 "\n", + id, trap_name(trap_t(t)), pc); } // switch to supervisor, set previous supervisor bit, disable traps @@ -201,8 +202,8 @@ void processor_t::disasm(insn_t insn, reg_t pc) { // the disassembler is stateless, so we share it static disassembler disasm; - printf("core %3d: 0x%016llx (0x%08x) %s\n", id, (unsigned long long)pc, - insn.bits, disasm.disassemble(insn).c_str()); + printf("core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n", + id, pc, insn.bits, disasm.disassemble(insn).c_str()); } void processor_t::set_pcr(int which, reg_t val) |